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公开(公告)号：US20210200679A1
公开(公告)日：2021-07-01
申请号：US17204534
申请日：2021-03-17
Applicant: QUALCOMM INCORPORATED
Inventor： Andrew Edmund TURNER , George PATSILARAS , Bohuslav RYCHLIK , Wesley James HOLLAND , Jeffrey SHABEL , Simon Peter William BOOTH
IPC: G06F12/0846 , G06F12/02 , G06F12/121 , G06F12/0891 , G06F12/0871 , G06F12/1072 , G06F12/0868
Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.
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2.发明申请公开(公告)号：US20170285705A1
公开(公告)日：2017-10-05
申请号：US15086054
申请日：2016-03-31
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward PODAIMA , Christophe Denis Bernard AVOINNE , Manokanthan SOMASUNDARAM , Sina DENA , Paul Christopher John WIERCIENSKI , Bohuslav RYCHLIK , Steven John HALTER , Jaya Prakash SUBRAMANIAM GANASAN , Myil RAMKUMAR , Dipt Ranjan PAL
CPC classification number: G06F1/266 , G06F1/10 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/08 , G06F2212/1028 , G06F2212/657 , G06F2212/683 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/171
Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
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公开(公告)号：US20220113901A1
公开(公告)日：2022-04-14
申请号：US17068293
申请日：2020-10-12
Applicant: QUALCOMM Incorporated
Inventor： Andrew Edmund TURNER , George PATSILARAS , Zhenbiao MA , Subbarao PALACHARLA , Bohuslav RYCHLIK , Tarek ZGHAL , Christopher KOOB
IPC: G06F3/06
Abstract: Various embodiments include methods and devices for managing optional commands. Some embodiments may include receiving an optional command from an optional command request device, determining whether the optional command can be implemented, and transmitting, to the optional command request device, an optional command no data response in response to determining that the optional command cannot be implemented.
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公开(公告)号：US20210174047A1
公开(公告)日：2021-06-10
申请号：US16703616
申请日：2019-12-04
Applicant: QUALCOMM Incorporated
Inventor： Wesley James HOLLAND , Rashmi KULKARNI , Ling Feng HUANG , Huang HUANG , Jeffrey SHABEL , Chih-Chi CHENG , Satish ANAND , Songhe CAI , Simon Peter William BOOTH , Bohuslav RYCHLIK
Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.
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公开(公告)号：US20230100036A1
公开(公告)日：2023-03-30
申请号：US17448864
申请日：2021-09-24
Applicant: QUALCOMM Incorporated
Inventor： Hee Jun PARK , Bohuslav RYCHLIK , Niraj Shantilal PALIWAL
Abstract: Certain aspects of the present disclosure provide techniques for improved hardware utilization. An input data tensor is divided into a first plurality of sub-tensors, and a plurality of logical sub-arrays in a physical multiply-and-accumulate (MAC) array is identified. For each respective sub-tensor of the first plurality of sub-tensors, the respective sub-tensor is mapped to a respective logical sub-array of the plurality of logical sub-arrays, and the respective sub-tensor is processed using the respective logical sub-array.
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Patent Agency Ranking
公开(公告)号：US20160342518A1
公开(公告)日：2016-11-24
申请号：US14716077
申请日：2015-05-19
Applicant: QUALCOMM Incorporated
Inventor： Hee Jun PARK , Bohuslav RYCHLIK , Steven S. THOMSON
CPC classification number: G06F12/0864 , G06F12/0802 , G06F12/0811 , G06F12/1027 , G06F17/5022 , G06F2212/283 , G06F2212/6032 , G06F2212/684
Abstract: Systems and methods for forecasting behavior of caches include a hypothetical cache. The hypothetical cache is configured to emulate cache behavior, and performance metrics for the hypothetical cache are determined, where the performance metrics may be based on cache hits/misses. Performance metrics for a real cache of a processor core of a processing system may also be similarly determined Behavior of the real cache is forecast based, at least, on performance metrics of the hypothetical cache, and in some cases, also on performance metrics of the real cache (e.g., based on a comparison of the performance metrics). Actions may be recommended and/or performed based on the forecast, where the actions include modifying the real cache size, associativity, or allocation for processor cores, migrating a task running in one processor cluster to another processor cluster, or for collecting data for the real cache for offline analysis.
Abstract translation: 用于预测缓存行为的系统和方法包括假设缓存。 虚拟缓存被配置为模拟缓存行为，并且确定假设高速缓存的性能度量，其中性能度量可以基于缓存命中/未命中。 还可以类似地确定处理系统的处理器核心的真实高速缓存的性能度量，至少基于假设高速缓存的性能度量，并且在某些情况下还基于性能度量来预测真实高速缓存的行为 实际缓存（例如，基于性能指标的比较）。 可以基于预测来推荐和/或执行动作，其中动作包括修改处理器核心的实际高速缓存大小，关联性或分配，将在一个处理器集群中运行的任务迁移到另一个处理器集群，或者为 真正的缓存用于离线分析。
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公开(公告)号：US20150370707A1
公开(公告)日：2015-12-24
申请号：US14313166
申请日：2014-06-24
Applicant: QUALCOMM Incorporated
Inventor： George PATSILARAS , Bohuslav RYCHLIK , Anwar ROHILLAH
CPC classification number: G06F12/0811 , G06F1/3275 , G06F1/3287 , G06F12/0815 , G06F12/0837 , G06F12/084 , G06F12/0848 , G06F2212/1024 , G06F2212/1028 , G06F2212/1056 , G06F2212/283 , G06F2212/314 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D10/171
Abstract: Systems and methods pertain to a multiprocessor system comprising disunited cache structures. A first private-information cache is coupled to a first processor of the multiprocessor system. The first private-information cache is configured to store information that is private to the first processor. A first shared-information cache which is disunited from the first private-information cache is also coupled to the first processor. The first shared-information cache is configured to store information that is shared/shareable between the first processor and one or more other processors of the multiprocessor system.
Abstract translation: 系统和方法涉及包含不完整缓存结构的多处理器系统。 第一私人信息缓存耦合到多处理器系统的第一处理器。 第一私人信息缓存被配置为存储对第一处理器是私有的信息。 与第一专用信息高速缓存分离的第一共享信息高速缓存也耦合到第一处理器。 第一共享信息缓存被配置为存储在第一处理器和多处理器系统的一个或多个其他处理器之间共享/共享的信息。
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8.发明申请METHOD AND APPARATUS FOR LOWERING BANDWIDTH AND POWER IN A CACHE USING READ WITH INVALIDATE 审中-公开降低带宽和功率的方法和设备使用读取无效的缓存公开(公告)号：US20150293847A1
公开(公告)日：2015-10-15
申请号：US14251628
申请日：2014-04-13
Applicant: QUALCOMM Incorporated
Inventor： George PATSILARAS , Moinul H. KHAN , Pankaj CHAURASIA , Bohuslav RYCHLIK , Feng WANG , Anwar Q. ROHILLAH , Subbarao PALACHARLA
CPC classification number: G06F12/0833 , G06F1/3275 , G06F12/0808 , G06F12/0868 , G06F12/126 , G06F12/128 , G06F2212/62 , Y02D10/13 , Y02D10/14
Abstract: Ephemeral data stored in a cache is read when needed but is not written to system memory so as to save power and bandwidth. In an embodiment, a no-writeback bit associated with the ephemeral data is set in response to a read-no-writeback instruction. Data in a cache line for which its no-writeback bit has been set is not written back into system memory. Accordingly, when evicting cache lines, if a cache line has a no-writeback bit set, then the data in that cache line is discarded without being written back to system memory.
Abstract translation: 存储在缓存中的短暂数据在需要时被读取，但不会写入系统内存，以节省功耗和带宽。 在一个实施例中，响应于无写回指令来设置与短暂数据相关联的无回写位。 已设置其无回写位的高速缓存行中的数据不会写入系统内存。 因此，当驱逐高速缓存行时，如果高速缓存行具有无回写位设置，则该高速缓存行中的数据被丢弃而不被写回系统存储器。
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9.发明申请公开(公告)号：US20190324512A1
公开(公告)日：2019-10-24
申请号：US16458940
申请日：2019-07-01
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward PODAIMA , Christophe Denis Bernard AVOINNE , Manokanthan SOMASUNDARAM , Sina DENA , Paul Christopher John WIERCIENSKI , Bohuslav RYCHLIK , Steven John HALTER , Jaya Prakash SUBRAMANIAM GANASAN , Myil RAMKUMAR , Dipti Ranjan PAL
IPC: G06F1/26 , G06F1/3287 , G06F1/324 , G06F1/3234 , G06F1/10
Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
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公开(公告)号：US20180336136A1
公开(公告)日：2018-11-22
申请号：US15645294
申请日：2017-07-10
Applicant: QUALCOMM Incorporated
Inventor： Farrukh HIJAZ , Andrew Edmund TURNER , Bohuslav RYCHLIK
IPC: G06F12/0862 , G06F12/02
Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for input/output-coherent look-ahead cache access on a computing device. The aspects may include intercepting, at a look-ahead device, a look-ahead request for data in a cache of a first input/output (I/O) device from a second I/O device, determining, by the look-ahead device, whether the data requested by the look-ahead request is stored in the cache, retrieving, by the look-ahead device, the data requested by the look-ahead request from the cache in response to determining that the data requested by the look-ahead request is stored in the cache, marking the data requested by the look-ahead request as invalid in the cache, and storing, by the look-ahead device, the retrieved data to a look-ahead buffer
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