公开(公告)号：US12235699B2

公开(公告)日：2025-02-25

申请号：US18166381

申请日：2023-02-08

Applicant: QUALCOMM Incorporated

Inventor： Vijayakumar Ashok Dibbad ,  Nikhil Ashok Bhelave ,  Jeffrey Gemar ,  Matthew Severson

IPC: G06F1/30

Abstract: Various embodiments include methods performed by a processor for managing voltage droop margins of a power distribution network (PDN). Various embodiments may include receiving, by a processor from a first client powered by a shared power rail within the PDN, a first requested performance corner, receiving, by the processor from a second client powered by the shared power rail, a second requested performance corner, determining by the processor a first peak current value based on the first requested performance corner, determining by the processor a second peak current value based on the second requested performance corner, determining by the processor a system voltage droop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN, and adjusting a voltage of the shared power rail based on the system voltage droop margin.

公开(公告)号：US11829172B2

公开(公告)日：2023-11-28

申请号：US17679811

申请日：2022-02-24

Applicant: QUALCOMM Incorporated

Inventor： Vijayakumar Ashok Dibbad ,  Fredrick Bontemps ,  Matthew Severson ,  Timothy Zoley

IPC: G05F1/62 ,  G05F1/56 ,  G01R19/165

CPC classification number: G05F1/56 ,  G01R19/16571 ,  G05F1/62

Abstract: An aspect of the disclosure relates to an apparatus including: an integrated circuit (IC) including one or more cores, and a current limit detection circuit; a voltage regulator; an inductor coupled between the voltage regulator and the one or more cores of the IC; and a current sensing circuit including inputs coupled across the inductor and an output coupled to the current limit detection circuit of the IC.

公开(公告)号：US11493980B1

公开(公告)日：2022-11-08

申请号：US17322402

申请日：2021-05-17

Applicant: QUALCOMM INCORPORATED

Inventor： Vijayakumar Ashok Dibbad ,  Bharat Kumar Rangarajan ,  Dipti Ranjan Pal ,  Keith Alan Bowman ,  Matthew Severson ,  Gordon Lee

IPC: G06F1/00 ,  G06F1/324 ,  H02H9/02 ,  G06F1/3296

Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.

公开(公告)号：US20250103130A1

公开(公告)日：2025-03-27

申请号：US18475371

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Matthew Severson ,  Gabriel Watkins ,  Vijayakumar Ashok Dibbad ,  Ronald Alton ,  Lai Xu ,  Jeffrey Gemar

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Power limiting in a processor-based system based on allocating power budgets for different sub-systems based on multiple time-based power limits is disclosed. The processor-based system has multiple power consuming sub-systems (e.g., non-processing unit (PU) and PU sub-systems) that demand and consume power from a power source of the processor-based system. To limit overall power consumption of the processor-based system over different time-based power limits, the processor-based system includes a power limiter circuit. The power limiter circuit is configured to manage multiple, different time-based (e.g., time constant) power limits for the processor-based system and to allocate corresponding power limit budgets to constrain power consumption of different sub-systems based on the multiple time-based power limits. The power limiter circuit can be configured to constrain power consumption of a PU sub-system to a total PU sub-system power limit budget based on the multiple time-based power limits.

公开(公告)号：US11630694B2

公开(公告)日：2023-04-18

申请号：US17148314

申请日：2021-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Vijayakumar Ashok Dibbad ,  Bharat Kumar Rangarajan ,  Prashanth Kumar Kakkireni ,  Srinivas Turaga

IPC: G06F9/46 ,  G06F9/48 ,  G06F1/28 ,  G06F9/52

Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.