公开(公告)号：US11733767B2

公开(公告)日：2023-08-22

申请号：US17359350

申请日：2021-06-25

Applicant: QUALCOMM Incorporated

Inventor： Prashanth Kumar Kakkireni ,  Matthew Severson ,  Kumar Kanti Ghosh ,  Shishir Joshi

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  H04L12/10

CPC classification number: G06F1/3296 ,  H04L12/10

Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

公开(公告)号：US11366508B1

公开(公告)日：2022-06-21

申请号：US17180071

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Prashanth Kumar Kakkireni ,  Naveen Kumar Narala ,  Sharon Graif

IPC: G06F1/3234 ,  G06F13/42 ,  G06F1/12 ,  G06F1/3206 ,  G06F1/26

Abstract: Systems, methods, and apparatus for power management are disclosed. A power management integrated circuit has a bus interface circuit configured to couple the power management integrated circuit to a shared communication bus, one or more regulator circuits configured to provide current to a managed device, and a controller. The controller is configured to determine that current consumption by the managed device exceeds a threshold level, generate an extended current level message to be transmitted over the shared communication bus to the managed device and transmit a time value with the extended current level message, the time value indicative of an elapsed time between generation of the extended current level message and start of transmission of the extended current level message.

公开(公告)号：US11630694B2

公开(公告)日：2023-04-18

申请号：US17148314

申请日：2021-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Vijayakumar Ashok Dibbad ,  Bharat Kumar Rangarajan ,  Prashanth Kumar Kakkireni ,  Srinivas Turaga

IPC: G06F9/46 ,  G06F9/48 ,  G06F1/28 ,  G06F9/52

Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.

公开(公告)号：US12099397B2

公开(公告)日：2024-09-24

申请号：US18069537

申请日：2022-12-21

Applicant: QUALCOMM Incorporated

Inventor： Prashanth Kumar Kakkireni ,  Matthew Severson ,  Ravi Jenkal ,  Gordon Lee ,  Kevin Bradley Citterelle ,  Ronald Alton ,  Anish Muttreja

IPC: G06F1/32 ,  G06F1/3296

CPC classification number: G06F1/3296

Abstract: Various embodiments include power management system methods including receiving, at a processor(s), a notification signal triggering the processor(s) to implement power usage mitigation at the processor(s), determining, by the processor(s), a mitigation amount of power rail power by which to mitigate current usage at a power rail based on a use case for the power rail, and implementing power usage mitigation at the processor(s) by the processor(s) sufficient to mitigate power usage at the power rail by the mitigation amount of power rail power. Power usage mitigation may include reducing processor(s) current usage: by a predefined amount; proportional to the amount a power rail current exceeds a power rail current threshold; by the amount of current exceeding a processor current threshold; or by a smallest amount between the amount a power rail current exceeds a power rail current threshold and the processor(s) current exceeds a processor current threshold.