公开(公告)号：US11424736B1

公开(公告)日：2022-08-23

申请号：US17485357

申请日：2021-09-25

Applicant: QUALCOMM Incorporated

Inventor： Keith Alan Bowman ,  Daniel Yingling ,  Dipti Ranjan Pal

IPC: H03K3/017 ,  H03K19/20 ,  H03K5/01 ,  G06F1/10 ,  H03K5/00

Abstract: Aspects of the present disclosure related to a method of phase extension using a delay circuit including delay devices coupled in series. The method includes receiving a clock signal, generating multiple delayed versions of the clock signal, wherein each of the delayed versions of the clock signal is delayed by a different number of the delay devices, and combining high phases or low phases of the delayed versions of the clock signal to obtain a combined clock signal.

公开(公告)号：US11264976B2

公开(公告)日：2022-03-01

申请号：US16906501

申请日：2020-06-19

Applicant: QUALCOMM Incorporated

Inventor： Fadi Hamdan ,  Keith Alan Bowman ,  Nadeem Eleyan ,  Xiang Li

IPC: H03K5/133 ,  H03L7/081 ,  H03K5/00

Abstract: Aspects of the disclosure are directed to adaptively delaying an input signal. In accordance with one aspect, an apparatus includes a plurality of delay units, wherein each of the plurality of delay units includes a substantially similar output load characteristic; a plurality of buffer units, wherein each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units.

公开(公告)号：US20190057757A1

公开(公告)日：2019-02-21

申请号：US16165549

申请日：2018-10-19

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C29/52 ,  G11C11/418 ,  G11C11/412 ,  H01L27/11 ,  G11C11/00 ,  G11C11/419

CPC classification number: G11C29/52 ,  G11C11/00 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

公开(公告)号：US10115481B2

公开(公告)日：2018-10-30

申请号：US15645355

申请日：2017-07-10

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C29/52 ,  G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  G11C11/00 ,  H01L27/11

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

公开(公告)号：US09947406B2

公开(公告)日：2018-04-17

申请号：US14860844

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Keith Alan Bowman ,  Francois Ibrahim Atallah ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C15/04 ,  G11C11/40 ,  H03K19/003 ,  H03K19/094

CPC classification number: G11C15/04 ,  G11C11/40 ,  H03K19/00315 ,  H03K19/094

Abstract: Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.

公开(公告)号：US20160247559A1

公开(公告)日：2016-08-25

申请号：US14862712

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C11/419

CPC classification number: G11C29/52 ,  G11C11/00 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

Abstract translation: 公开了采用P型场效应晶体管（PFET）读端口的存储位单元的读辅助电路。 还公开了相关的存储器系统和方法。 已经观察到，随着节点技术的尺寸缩小，PFET驱动电流（即，驱动强度）超过用于相似尺寸的FET的N型FET（NFET）驱动电流。 在这方面，在一方面，期望提供与NFET读取端口相反的具有PFET读取端口的存储器位单元，以将存储器读取时间增加到存储器位单元，从而提高存储器读取性能。 为了减轻或避免在读取存储器位单元时可能发生的读取干扰条件，为具有PFET读取端口的存储器单元提供读取辅助电路。

公开(公告)号：US12224752B1

公开(公告)日：2025-02-11

申请号：US18354374

申请日：2023-07-18

Applicant: QUALCOMM Incorporated

Inventor： Yimai Peng ,  Robert Joseph Vachon ,  Daniel Yingling ,  Keith Alan Bowman

IPC: G06F1/04 ,  H03K3/037 ,  H03K17/00 ,  H03K19/21

Abstract: An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

公开(公告)号：US11031075B2

公开(公告)日：2021-06-08

申请号：US16406749

申请日：2019-05-08

Applicant: QUALCOMM Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  Jihoon Jeong

IPC: G11C11/419 ,  G11C11/418

Abstract: A high bandwidth register file circuit that significantly reduces the shared local read bitline RC delay to enable ultra-high performance PRFs with high port counts. In one example, the register file circuit includes read stack nfets in a multiplexer circuit instead of the memory cell causing the local read bitline RC to be independent of the number of read and write ports of the memory cell.

公开(公告)号：US10163490B2

公开(公告)日：2018-12-25

申请号：US14862483

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong

IPC: G11C11/419 ,  G11C7/06 ,  G11C7/08 ,  G11C11/412 ,  G11C11/418

Abstract: P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells (“bit cells”). Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sense bit line voltage(s) of the bit cells for reading the data stored in the bit cells. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-effect Transistor (NFET) drive current due for like-dimensioned FETs. In this regard, in one aspect, PFET-based sense amplifiers are provided in a memory system to increase memory read times to the bit cells, and thus improve memory read performance.

公开(公告)号：US09741452B2

公开(公告)日：2017-08-22

申请号：US14862712

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C29/52 ,  G11C11/419 ,  G11C11/00 ,  G11C11/412 ,  G11C11/418

CPC classification number: G11C29/52 ,  G11C11/00 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.