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    LOW-POWER AND LOW-LATENCY DEVICE ENUMERATION WITH CARTESIAN ADDRESSING
    2.
    发明申请
    LOW-POWER AND LOW-LATENCY DEVICE ENUMERATION WITH CARTESIAN ADDRESSING 有权
    低功耗和低功耗设备与卡特彼勒寻址

    公开(公告)号：US20160285968A1

    公开(公告)日：2016-09-29

    申请号：US15077841

    申请日：2016-03-22

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  James Panian ,  Richard Wietfeldt

    IPC: H04L29/08 ,  H04L29/12

    CPC classification number: H04L67/1091 ,  G06F13/4247 ,  G06F2213/0052 ,  H04L61/2007 ,  H04L61/604

    Abstract: An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.

    Abstract translation: 提供了一种枚举技术，其不需要将通过P2P链接连接到主机设备的从设备的地址预先分配。 关于设备之间的任何P2P链路，一个设备具有主接口，其余设备具有从接口。 为了区分主从接口，可以使用主/从状态位。 每个P2P链路具有可以与相应接口（从属或主机）的状态位连接以形成节点ID的链路ID。 主设备从每个从设备接收代表从设备的节点ID的级联和从设备与主设备之间的任何介入接口的节点ID的唯一的级联地址。 然后，主机设备为每个从设备分配唯一的笛卡尔地址。

    LOW-POWER AND LOW-LATENCY DEVICE ENUMERATION WITH CARTESIAN ADDRESSING
    3.
    发明申请
    LOW-POWER AND LOW-LATENCY DEVICE ENUMERATION WITH CARTESIAN ADDRESSING 审中-公开

    公开(公告)号：US20180241816A1

    公开(公告)日：2018-08-23

    申请号：US15956708

    申请日：2018-04-18

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  James Panian ,  Richard Wietfeldt

    IPC: H04L29/08 ,  H04L29/12 ,  G06F13/42

    CPC classification number: H04L67/1091 ,  G06F13/4247 ,  G06F2213/0052 ,  H04L61/2007 ,  H04L61/604

    Abstract: An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.

    Low-power and low-latency device enumeration with cartesian addressing
    4.
    发明授权
    Low-power and low-latency device enumeration with cartesian addressing 有权

    公开(公告)号：US09979782B2

    公开(公告)日：2018-05-22

    申请号：US15077841

    申请日：2016-03-22

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  James Panian ,  Richard Wietfeldt

    IPC: H04L29/08 ,  H04L29/12 ,  G06F13/42

    CPC classification number: H04L67/1091 ,  G06F13/4247 ,  G06F2213/0052 ,  H04L61/2007 ,  H04L61/604

    Abstract: An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.

    CLOCK-FREE DUAL-DATA-RATE LINK WITH BUILT-IN FLOW CONTROL
    5.
    发明申请
    CLOCK-FREE DUAL-DATA-RATE LINK WITH BUILT-IN FLOW CONTROL 有权
    具有内置流量控制的无时钟双数据速率链路

    公开(公告)号：US20160098073A1

    公开(公告)日：2016-04-07

    申请号：US14864586

    申请日：2015-09-24

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Wietfeldt ,  James Panian

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F13/4286 ,  G06F13/4295

    Abstract: A dual-data-rate interface is provided that includes a transmitter driving a transmit pin coupled to a receive pin of a receiver. The receiver drives its receive pin with cycles of a fetch clock. The transmitter responds to each edge of the fetch clock by transmitting a bit over the transmit pin to the receiver.

    Abstract translation: 提供了一种双数据速率接口，其包括驱动耦合到接收器的接收引脚的发送引脚的发射器。 接收器通过提取时钟周期驱动其接收引脚。 发送器通过将发送引脚上的位发送到接收器来响应获取时钟的每个边沿。

    Low-power and low-latency device enumeration with cartesian addressing
    6.
    发明授权
    Low-power and low-latency device enumeration with cartesian addressing 有权

    公开(公告)号：US10924541B2

    公开(公告)日：2021-02-16

    申请号：US15956708

    申请日：2018-04-18

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  James Panian ,  Richard Wietfeldt

    IPC: H04L29/08 ,  G06F13/42 ,  H04L29/12

    Abstract: An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.

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