公开(公告)号：US20210173419A1

公开(公告)日：2021-06-10

申请号：US17088066

申请日：2020-11-03

Applicant: QUALCOMM Incorporated

Inventor： Matthew SEVERSON ,  Timothy ZOLEY ,  Lipeng CAO ,  Kevin Bradley CITTERELLE ,  Richard Gerard HOFMANN

IPC: G05F1/46 ,  H05K1/18 ,  G01R19/00 ,  G01K7/18

Abstract: An apparatus including a printed circuit board (PCB) including a sense resistor; and an integrated circuit (IC) mounted on the PCB, wherein at least a portion of the IC draws current from a power rail, wherein the sense resistor is coupled between the power rail and the IC, wherein the sense resistor is configured to produce a sense voltage in response to the current drawn by the at least portion of the IC, and wherein the IC includes a current sensor configured to generate a signal indicative of the current drawn by the at least portion of the IC based on the sense voltage.

公开(公告)号：US20240085971A1

公开(公告)日：2024-03-14

申请号：US17941535

申请日：2022-09-09

Applicant: QUALCOMM Incorporated

Inventor： Lipeng CAO

IPC: G06F1/3293 ,  G06F1/3215

CPC classification number: G06F1/3293 ,  G06F1/3215

Abstract: Aspects relate to limits management for a processor power distribution network. In an aspect, an electronic device has a processor with a processing core that is coupled to a power rail. The power rail is external to the processor. A current sensor is associated with the output of the power rail and configured to produce current sensor readings. A state-space unit is coupled to the current sensor. The state-space unit has a predictive model to apply the current sensor readings to the predictive model to predict a current budget for the processing core. A limit manager is configured to generate a current limit in response to the current budget. The limit manager limits a current draw of the processing core in response to the current limit.

公开(公告)号：US20190391608A1

公开(公告)日：2019-12-26

申请号：US16016410

申请日：2018-06-22

Applicant: QUALCOMM Incorporated

Inventor： Lipeng CAO ,  Rajeev JAIN ,  Harshat PANT ,  Byron Glenn MURPHY

IPC: G05F1/59

Abstract: A power multiplexer system including a power mux controller, wherein the power mux controller generates at least one non-regulated control signal; a regulator coupled to the power mux controller, wherein the regulator generates a reference voltage and wherein the reference voltage is used for generating a regulated control signal; and at least one power multiplexer tile coupled to the regulator, wherein each of the at least one power multiplexer tile includes a first branch comprising a first plurality of transistors and a second branch comprising a second plurality of transistors, and wherein enabling or disabling one or more of the first plurality of transistors is based on either the at least one non-regulated control signal or the regulated control signal.

公开(公告)号：US20170085253A1

公开(公告)日：2017-03-23

申请号：US14861503

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Lipeng CAO ,  Jeffrey GEMAR ,  Ramaprasath VILANGUDIPITCHAI

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/356008 ,  H03K3/3562

Abstract: Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.