公开(公告)号：US10700683B1

公开(公告)日：2020-06-30

申请号：US16114524

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Sumit Rao

IPC: H03K19/00 ,  H03K5/08 ,  H03K5/24 ,  H03K19/003 ,  H03K19/0185 ,  G06F1/26 ,  H03K3/3565 ,  H03K17/10

Abstract: Aspects generally relate to receivers, and in particular to a receiver that converts a high-voltage input signal into a low-voltage signal. The high voltage input signal is split into a upper portion and a lower portion. The upper portion is coupled to a high input receiver that is powered by dynamic supply shifters that can vary supply voltage during operation to optimize switching.

公开(公告)号：US09735763B1

公开(公告)日：2017-08-15

申请号：US15083030

申请日：2016-03-28

Applicant: QUALCOMM Incorporated

Inventor： Wilson Chen ,  Chiew-Guan Tan ,  Sumit Rao

IPC: H03K5/08 ,  H03K19/003 ,  H03K5/24

CPC classification number: H03K5/08 ,  G06F13/4072 ,  H03K5/24 ,  H03K19/00315 ,  H03K19/018514

Abstract: An input receiver for stepping down a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain includes a waveform splitter. The waveform splitter splits the high power domain input signal into a high voltage signal and a low voltage signal. A high voltage input receiver receives the high voltage signal to produce a received high voltage that is level shifted into a first input signal. A low voltage input receiver receives the low voltage signal to produce a second input signal. A logic circuit generates the output signal from the first input signal and the second input signal.

公开(公告)号：US11251794B2

公开(公告)日：2022-02-15

申请号：US17008068

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Sumit Rao ,  Wilson Jianbo Chen ,  Chiew-Guan Tan

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/003

Abstract: An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.

公开(公告)号：US10892760B1

公开(公告)日：2021-01-12

申请号：US16653391

申请日：2019-10-15

Applicant: QUALCOMM Incorporated

Inventor： Sumit Rao ,  Wilson Jianbo Chen ,  Chiew-Guan Tan

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/003

Abstract: An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.