公开(公告)号：US20230140388A1

公开(公告)日：2023-05-04

申请号：US17513463

申请日：2021-10-28

Applicant: Quanta Computer Inc.

Inventor： Wei-Hung LIN ,  Yen-Ping TUNG

IPC: G06F13/42

Abstract: A computing system includes a processing unit and a network device. The processing unit includes a first baseboard management controller (BMC), an external network interface coupled to the first BMC, and a first internal network interface coupled to the first BMC. The network device includes a second BMC and a second internal network interface coupled to the second BMC. The second internal network interface of the network device is connected to the first internal network interface of the processing unit. The first BMC is configured to transfer data between an external network and the second BMC via (i) the external network interface, (ii) the first internal network interface, and (iii) the second internal network interface.

公开(公告)号：US20240220113A1

公开(公告)日：2024-07-04

申请号：US18147124

申请日：2022-12-28

Applicant: Quanta Computer Inc.

Inventor： Wei-Hung LIN ,  Yen-Ping TUNG ,  Han-Chuan TSAI

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679

Abstract: An example computer-implemented method for synchronously programming multiple memory modules includes sending one or more instructions to each of the memory modules to perform a first data operation associated with a computer software update. In response to determining that each of the memory modules have received the first instructions to perform the first data operation, time is spent waiting for the first data operation to be completed at each of the memory modules. One or more instructions are also sent to each of the memory modules to perform a second data operation associated with the computer software update. In response to determining that each of the memory modules have received the second instructions to perform the second data operation, time is spent waiting for the second data operation to be completed at each of the memory modules. Furthermore, the data is validated across the memory modules.

公开(公告)号：US20240193104A1

公开(公告)日：2024-06-13

申请号：US18156251

申请日：2023-01-18

Applicant: Quanta Computer Inc.

Inventor： Han-Chuan TSAI ,  Wei-Hung LIN ,  Yen-Ping TUNG ,  Sz-Chin SHIH

IPC: G06F13/16

CPC classification number: G06F13/1652 ,  G06F2213/0016 ,  G06F2213/3808

Abstract: A system and method for a configurable computer system architecture is disclosed. The computer system architecture includes a power distribution board including a configuration identification strapping. The architecture includes a first node having a first processor and a first baseboard management controller (BMC) coupled to the power distribution board via an internal communication channel. A second node, identical to the first node, has a second processor and a second BMC coupled to the power distribution board via the internal communication channel. The configuration identification strapping is one of a first configuration readable by the first and second BMCs with two nodes operating as independent devices, or a second configuration readable by the first and second BMCs with two nodes operating as a single device. The first BMC serves as a master BMC and the second BMC serves as a slave BMC in the second configuration.

公开(公告)号：US20230133726A1

公开(公告)日：2023-05-04

申请号：US17513548

申请日：2021-10-28

Applicant: Quanta Computer Inc.

Inventor： Tzu-Heng WEN ,  Yen-Ping TUNG ,  Wei-Hung LIN

IPC: G06F21/57 ,  G06F21/76 ,  H04L9/32 ,  G06F3/06

Abstract: A method and system to ensure correct firmware image execution in a computer system. The computer system has a processor executing a basic input/output system (BIOS) and a baseboard management controller (BMC). A first flash memory device is coupled to the processor storing a BIOS firmware image and a project name. A second flash memory device is coupled to the BMC storing a BMC firmware image and the project name. A programmable logic device is coupled to the first and second flash memory devices. The programmable logic device including a non-volatile memory storing a project name. The programmable logic device is configured to execute a Platform Firmware Resilience routine to compare the project name of the BIOS firmware image and the project name of the BMC firmware image with the stored project name before starting the BMC or executing the BIOS firmware image by the processor.