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公开(公告)号：US20150033058A1
公开(公告)日：2015-01-29
申请号：US14455814
申请日：2014-08-08
Applicant: Quanta Computer Inc.
Inventor： Le-Sheng CHOU , Sz-Chin SHIH
IPC: G06F1/32 , H04L12/931
CPC classification number: G06F1/3287 , G06F11/00 , H04L49/356
Abstract: A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node includes a network port, a network chip and a control unit. The network port is connected to the network switch via a cable. The network chip detects the cable to obtain a connection state with the external network at the server node after the network switch is started, and accordingly outputs a connection state signal. The control unit turns on or shuts down the server node according to the connection state signal and an on/off state of the server node.
Abstract translation: 提供了包括网络交换机和多个服务器节点的服务器集群。 网络交换机连接到外部网络。 每个服务器节点包括网络端口，网络芯片和控制单元。 网络端口通过电缆连接到网络交换机。 网络芯片检测到电缆在网络切换启动后在服务器节点处获得与外部网络的连接状态，从而输出连接状态信号。 控制单元根据连接状态信号和服务器节点的开/关状态打开或关闭服务器节点。
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公开(公告)号：US20240385610A1
公开(公告)日：2024-11-21
申请号：US18319676
申请日：2023-05-18
Applicant: Quanta Computer Inc.
Inventor： Le-Sheng CHOU , Sz-Chin SHIH , Shuen-Hung WANG , Hsien-Chang LI
IPC: G05B23/02
Abstract: A computing system includes one or more electronic components, a first programmable device, and a baseboard management controller (BMC). The first programmable device is communicatively coupled to a first subset of the one or more electronic components. The first programmable device is configured to detect event activities associated with the first subset and to store the event activities as stored first event data. The BMC includes a system event log. The BMC is communicatively coupled to the first programmable device. The BMC is configured to receive the stored first event data and to write the stored first event data in the system event log.
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公开(公告)号：US20170168943A1
公开(公告)日：2017-06-15
申请号：US14965975
申请日：2015-12-11
Applicant: Quanta Computer Inc.
Inventor： Le-Sheng CHOU , Sz-Chin SHIH
IPC: G06F12/08 , H01R24/28 , H01R24/20 , H01R12/70 , G06F12/12 , G06F13/40 , G06F13/42 , G06F13/16 , G06F12/02 , G06F1/18 , H01R12/72
CPC classification number: G06F12/0833 , G06F1/185 , G06F1/187 , G06F12/0246 , G06F12/12 , G06F12/128 , G06F13/1673 , G06F13/4022 , G06F13/4291 , G06F2212/621 , G06F2212/7206 , H01R12/7076 , H01R12/72 , H01R24/20 , H01R24/28
Abstract: A component carrier with a housing and a converter board disposed within the housing. The converter board including a U.2 connector, an M.2 connector configured to receive an M.2 solid state drive having a cache memory, and a capacitor. The capacitor provides backup power for a power loss protection system allowing flush cache storage. The housing configured to receive one or more M.2 solid state drives coupled with the converter board.
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公开(公告)号：US20170091133A1
公开(公告)日：2017-03-30
申请号：US14865955
申请日：2015-09-25
Applicant: Quanta Computer Inc.
Inventor： Le-Sheng CHOU , Sz-Chin SHIH
CPC classification number: G06F13/4022 , G06F13/385 , G06F13/4282
Abstract: A system for sharing input/output using universal sleds includes a first universal sled that includes a first switch and a first universal node, and a second universal sled that includes a second switch and a second universal node, where the first universal sled and second universal sled have interchangeable physical dimensions. The midplane board includes a management processor and a midplane switch. The system further includes an input/output sled and a bus that connects the first universal sled, the second universal sled, the midplane board, and the input/output sled.
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公开(公告)号：US20170153660A1
公开(公告)日：2017-06-01
申请号：US14953975
申请日：2015-11-30
Applicant: Quanta Computer Inc.
Inventor： Le-Sheng CHOU , Sz-Chin SHIH
CPC classification number: G06F1/12 , G06F13/4291
Abstract: A method for automatic clock configurations is performed by a system having a host and a peripheral device. The host indicates on a first general-purpose input/output (GPIO) of a peripheral interface connecting the host and the peripheral device, whether the host supports a first clock configuration. The peripheral device receives from the first GPIO whether the host supports the first clock configuration. The peripheral device selects, in response to the host supporting the first clock configuration, use of a local clock of the peripheral device. The peripheral device selects, in response to the host not supporting the first clock configuration, use of a common clock of the host.
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Patent Agency Ranking
公开(公告)号：US20170091042A1
公开(公告)日：2017-03-30
申请号：US14865938
申请日：2015-09-25
Applicant: Quanta Computer Inc.
Inventor： Le-Sheng CHOU , Sz-Chin SHIH
CPC classification number: G06F12/0868 , G06F11/1441 , G06F11/2015 , G06F12/0804 , G06F13/16 , G06F21/81 , G06F2212/1032 , G06F2212/281 , G06F2212/313 , G06F2212/60
Abstract: Embodiments generally relate to power loss protection in a computing system. The present technology discloses techniques that enable a graceful removal of power using a microcontroller controller in communication with a backup power supply. By utilizing a relative inexpensive microcontroller, the present technology can achieve data protection for a large number of storage devices at a low cost.
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公开(公告)号：US20160308717A1
公开(公告)日：2016-10-20
申请号：US14686217
申请日：2015-04-14
Applicant: Quanta Computer Inc.
Inventor： Le-Sheng CHOU , Sz-Chin SHIH
CPC classification number: H04L41/0816 , G06F13/128 , G06F13/385 , H04L41/20
Abstract: A controller in a server system can determine whether to share a network connection of the server system. In response to determining to share the network connection, the controller can disable a dedicated network connection between the controller and a network interface controller (NIC) in the server system, enable a first shared network connection between the controller and a computing module in the server system, and enable a second shared network connection between the computing module and the NIC. In response to determining not to share the network connection, the controller can enable the dedicated network connection between the controller and the NIC.
Abstract translation: 服务器系统中的控制器可以确定是否共享服务器系统的网络连接。 响应于确定共享网络连接，控制器可以禁用控制器与服务器系统中的网络接口控制器（NIC）之间的专用网络连接，使得控制器与服务器中的计算模块之间的第一共享网络连接 系统，并且在计算模块和NIC之间启用第二共享网络连接。 响应于确定不共享网络连接，控制器可以启用控制器和NIC之间的专用网络连接。
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公开(公告)号：US20160266560A1
公开(公告)日：2016-09-15
申请号：US14641945
申请日：2015-03-09
Applicant: Quanta Computer Inc.
Inventor： Le-Sheng CHOU , Sz-Chin SHIH
IPC: G05B19/042 , G05B19/10
CPC classification number: G05B19/042 , G05B19/106 , G05B2219/25425 , G06F1/206
Abstract: Embodiments generally relate to thermal management in a multi-node computing device. The present technology discloses techniques that can receive multiple control signals from multiple computing nodes, each of the control signals being associated with a fan duty request, which is a request for a fan duty needed to keep a related computing node operating within a predetermined temperature range. The logic controller can rank the received control signals and select a control signal that requests a highest fan duty; lastly, the logic controller can cause multiple cooling fans to operate at the selected highest fan duty.
Abstract translation: 实施例通常涉及多节点计算设备中的热管理。 本技术公开了可以从多个计算节点接收多个控制信号的技术，每个控制信号与风扇占空请求相关联，该风扇占空请求是对相关计算节点在预定温度范围内运行所需的风扇占空比 。 逻辑控制器可对所接收的控制信号进行排序，并选择请求最高风扇占空比的控制信号; 最后，逻辑控制器可以使多个冷却风扇以选定的最高风扇功率运行。
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公开(公告)号：US20240193104A1
公开(公告)日：2024-06-13
申请号：US18156251
申请日：2023-01-18
Applicant: Quanta Computer Inc.
Inventor： Han-Chuan TSAI , Wei-Hung LIN , Yen-Ping TUNG , Sz-Chin SHIH
IPC: G06F13/16
CPC classification number: G06F13/1652 , G06F2213/0016 , G06F2213/3808
Abstract: A system and method for a configurable computer system architecture is disclosed. The computer system architecture includes a power distribution board including a configuration identification strapping. The architecture includes a first node having a first processor and a first baseboard management controller (BMC) coupled to the power distribution board via an internal communication channel. A second node, identical to the first node, has a second processor and a second BMC coupled to the power distribution board via the internal communication channel. The configuration identification strapping is one of a first configuration readable by the first and second BMCs with two nodes operating as independent devices, or a second configuration readable by the first and second BMCs with two nodes operating as a single device. The first BMC serves as a master BMC and the second BMC serves as a slave BMC in the second configuration.
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公开(公告)号：US20220197848A1
公开(公告)日：2022-06-23
申请号：US17127279
申请日：2020-12-18
Applicant: QUANTA COMPUTER INC.
Inventor： Le-Sheng CHOU , Sz-Chin SHIH
Abstract: A system and device for expanding accessible memory of a processor is provided. An interposer is coupled to the processor and a memory module. The interposer is coupled to a first connection and a second connection. The interposer includes a memory controller circuit. The memory controller circuit receives signals from the processor, using the first connection, and transmits the received signals to the memory module, using the second connection. The interposer expands memory access without an unnecessary second processor.
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