公开(公告)号：US20230140388A1

公开(公告)日：2023-05-04

申请号：US17513463

申请日：2021-10-28

Applicant: Quanta Computer Inc.

Inventor： Wei-Hung LIN ,  Yen-Ping TUNG

IPC: G06F13/42

Abstract: A computing system includes a processing unit and a network device. The processing unit includes a first baseboard management controller (BMC), an external network interface coupled to the first BMC, and a first internal network interface coupled to the first BMC. The network device includes a second BMC and a second internal network interface coupled to the second BMC. The second internal network interface of the network device is connected to the first internal network interface of the processing unit. The first BMC is configured to transfer data between an external network and the second BMC via (i) the external network interface, (ii) the first internal network interface, and (iii) the second internal network interface.

公开(公告)号：US20230075055A1

公开(公告)日：2023-03-09

申请号：US17447159

申请日：2021-09-08

Applicant: Quanta Computer Inc.

Inventor： Jhao-Han CHEN ,  Yen-Ping TUNG

IPC: G06F3/06

Abstract: A system to monitor the condition of a flash memory device such as flash memory devices that store hardware settings for a BIOS or system logs in a computer system is disclosed. The flash memory device is controlled by a flash memory driver. A controller provides a command via a file system to write data to the flash memory driver. A flash memory module interfaces with the flash memory driver. The flash memory module is configured to determine whether the command to write data requires a block erase of the flash memory device. The flash memory module determines an erase time from when a command to erase a block is sent to when a status of write ready is sent by the flash memory device.

公开(公告)号：US20240220113A1

公开(公告)日：2024-07-04

申请号：US18147124

申请日：2022-12-28

Applicant: Quanta Computer Inc.

Inventor： Wei-Hung LIN ,  Yen-Ping TUNG ,  Han-Chuan TSAI

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679

Abstract: An example computer-implemented method for synchronously programming multiple memory modules includes sending one or more instructions to each of the memory modules to perform a first data operation associated with a computer software update. In response to determining that each of the memory modules have received the first instructions to perform the first data operation, time is spent waiting for the first data operation to be completed at each of the memory modules. One or more instructions are also sent to each of the memory modules to perform a second data operation associated with the computer software update. In response to determining that each of the memory modules have received the second instructions to perform the second data operation, time is spent waiting for the second data operation to be completed at each of the memory modules. Furthermore, the data is validated across the memory modules.

公开(公告)号：US20170317892A1

公开(公告)日：2017-11-02

申请号：US15140259

申请日：2016-04-27

Applicant: Quanta Computer Inc.

Inventor： Yen-Ping TUNG

IPC: H04L12/24

Abstract: Systems, methods, and computer-readable storage devices for reducing the amount of management ports (and associated cabling) for a top-of-rack server environment. Whereas other server management configurations have cabling connecting each node in multiple multi-node chassis in a server rack to a top-of-rack, systems configured as described herein designate a single node as a point of communication for the multi-node chassis. The designated node forwards communications for all nodes in the chassis to a chassis management controller, which acts as a distribution point for all communications within the multi-node chassis, with the benefit of only a single connection being required between the multi-node chassis and the top of rack switch.

公开(公告)号：US20230161658A1

公开(公告)日：2023-05-25

申请号：US17534717

申请日：2021-11-24

Applicant: QUANTA COMPUTER INC.

Inventor： Yen-Ping TUNG

IPC: G06F11/07 ,  G06F13/42 ,  G06F9/38 ,  G06F11/14

CPC classification number: G06F11/0772 ,  G06F11/0784 ,  G06F13/4282 ,  G06F9/3877 ,  G06F11/141

Abstract: Embodiments of this disclosure are directed towards a method of logging messages in a baseboard management controller (BMC) system. The method includes powering on a processing chip of the BMC system, wherein the processing chip has a main processor and a co-processor that is communicatively coupled to a non-transitory processor-readable memory device and snooping interface. The method further includes booting up the co-processor, and initiating a storage portion of the non-transitory processor-readable memory device the snooping interface. The method further includes triggering a boot-up of the main processor, and receiving, via the snooping interface, the messages redirected from a communication interface of the BMC system.

公开(公告)号：US20220414045A1

公开(公告)日：2022-12-29

申请号：US17450144

申请日：2021-10-06

Applicant: Quanta Computer Inc.

Inventor： Chi-Ling YANG ,  Yen-Ping TUNG

IPC: G06F13/42 ,  G06F13/16

Abstract: A baseboard management controller (BMC) system adaptable to support multiple computer platforms is disclosed. The BMC system has a BMC CPU chip including a processor executing firmware. The BMC CPU chip is coupled via an external bus to an interface chip. The interface chip includes input/output interfaces for different communication protocols to interface with components on a computer node.

公开(公告)号：US20170315951A1

公开(公告)日：2017-11-02

申请号：US15140220

申请日：2016-04-27

Applicant: Quanta Computer Inc.

Inventor： Yen-Ping TUNG

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4081 ,  G06F13/00 ,  G06F13/382 ,  G06F13/385 ,  G06F13/4282 ,  H04L41/00

Abstract: In the maintenance of rack system, a computing device may implement a plurality of smart plugs and a communication bus in a system. A smart plug may be plugged into a server node for communication between a management node and a designated server node. The communication bus may be coupled to the smart plugs for transmitting I2C packets. A server node may be associated with a corresponding smart plug that includes a unique address on the communication bus. The smart plug may be configured to receive a message via the communication bus. The smart plug is configured to determine whether the request is addressed to a unique address associated with the smart plug. Upon determining that the message is addressed to the unique address, the smart plug may reformat the request compatible with server node port using the local address. Reformatting request may depend on types of server node ports.

公开(公告)号：US20240193104A1

公开(公告)日：2024-06-13

申请号：US18156251

申请日：2023-01-18

Applicant: Quanta Computer Inc.

Inventor： Han-Chuan TSAI ,  Wei-Hung LIN ,  Yen-Ping TUNG ,  Sz-Chin SHIH

IPC: G06F13/16

CPC classification number: G06F13/1652 ,  G06F2213/0016 ,  G06F2213/3808

Abstract: A system and method for a configurable computer system architecture is disclosed. The computer system architecture includes a power distribution board including a configuration identification strapping. The architecture includes a first node having a first processor and a first baseboard management controller (BMC) coupled to the power distribution board via an internal communication channel. A second node, identical to the first node, has a second processor and a second BMC coupled to the power distribution board via the internal communication channel. The configuration identification strapping is one of a first configuration readable by the first and second BMCs with two nodes operating as independent devices, or a second configuration readable by the first and second BMCs with two nodes operating as a single device. The first BMC serves as a master BMC and the second BMC serves as a slave BMC in the second configuration.

公开(公告)号：US20230133726A1

公开(公告)日：2023-05-04

申请号：US17513548

申请日：2021-10-28

Applicant: Quanta Computer Inc.

Inventor： Tzu-Heng WEN ,  Yen-Ping TUNG ,  Wei-Hung LIN

IPC: G06F21/57 ,  G06F21/76 ,  H04L9/32 ,  G06F3/06

Abstract: A method and system to ensure correct firmware image execution in a computer system. The computer system has a processor executing a basic input/output system (BIOS) and a baseboard management controller (BMC). A first flash memory device is coupled to the processor storing a BIOS firmware image and a project name. A second flash memory device is coupled to the BMC storing a BMC firmware image and the project name. A programmable logic device is coupled to the first and second flash memory devices. The programmable logic device including a non-volatile memory storing a project name. The programmable logic device is configured to execute a Platform Firmware Resilience routine to compare the project name of the BIOS firmware image and the project name of the BMC firmware image with the stored project name before starting the BMC or executing the BIOS firmware image by the processor.

公开(公告)号：US20170295053A1

公开(公告)日：2017-10-12

申请号：US15096032

申请日：2016-04-11

Applicant: Quanta Computer Inc.

Inventor： Yen-Ping TUNG

IPC: H04L12/24 ,  H04L12/751

Abstract: Systems, methods, and computer-readable media for managing nodes through virtual rack management modules. A system can have a first rack that includes a first top-of-rack (ToR) switch and a first group of nodes. The first ToR switch can be connected to the first group of nodes. The system can also have a second rack that includes a second ToR switch and a second group of nodes. The second ToR switch can be connected to the second group of nodes, and the second ToR switch can be connected to the first ToR switch. Furthermore, the system can include a rack management node that executes a hypervisor. The hypervisor can run a first virtual rack management module (vRMM) and a second vRMM. The first vRMM and the second vRMM can manage the first group of nodes and the second group of nodes, respectively.