公开(公告)号：US20210193197A1

公开(公告)日：2021-06-24

申请号：US16953207

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20220343956A1

公开(公告)日：2022-10-27

申请号：US17705039

申请日：2022-03-25

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US10902891B2

公开(公告)日：2021-01-26

申请号：US16805529

申请日：2020-02-28

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20200294559A1

公开(公告)日：2020-09-17

申请号：US16805529

申请日：2020-02-28

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US12249392B2

公开(公告)日：2025-03-11

申请号：US18388680

申请日：2023-11-10

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C16/04 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10

Abstract: A memory controller includes a register to store phase offset value. The phase offset value represents a phase relationship between a memory request signal component and a reference signal. The phase offset value is established through write and read back testing. Transmit circuitry applies the phase offset value in launching the memory request signal component from the IC memory controller to an IC memory device.

公开(公告)号：US20240177747A1

公开(公告)日：2024-05-30

申请号：US18388680

申请日：2023-11-10

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F12/00 ,  G06F13/16

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US10593379B2

公开(公告)日：2020-03-17

申请号：US16109607

申请日：2018-08-22

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C8/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US10062421B2

公开(公告)日：2018-08-28

申请号：US15626097

申请日：2017-06-17

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C8/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US08638637B2

公开(公告)日：2014-01-28

申请号：US13720720

申请日：2012-12-19

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C8/00

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Abstract translation: 具有时间交错请求信号输出的存储器控​​制器。 产生第一定时信号，同时产生具有相对于第一定时信号的第一相位差的第二定时信号。 响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

公开(公告)号：US20130111176A1

公开(公告)日：2013-05-02

申请号：US13720720

申请日：2012-12-19

Applicant: RAMBUS INC.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G06F12/00

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.