公开(公告)号：US20220084571A1

公开(公告)日：2022-03-17

申请号：US17305654

申请日：2021-07-12

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/02

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

公开(公告)号：US11062748B2

公开(公告)日：2021-07-13

申请号：US16459330

申请日：2019-07-01

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/02

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

公开(公告)号：US20210193197A1

公开(公告)日：2021-06-24

申请号：US16953207

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US10339990B2

公开(公告)日：2019-07-02

申请号：US15665312

申请日：2017-07-31

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G01C7/02 ,  G11C7/22 ,  G06F13/16 ,  G11C7/02

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

公开(公告)号：US12249392B2

公开(公告)日：2025-03-11

申请号：US18388680

申请日：2023-11-10

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C16/04 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10

Abstract: A memory controller includes a register to store phase offset value. The phase offset value represents a phase relationship between a memory request signal component and a reference signal. The phase offset value is established through write and read back testing. Transmit circuitry applies the phase offset value in launching the memory request signal component from the IC memory controller to an IC memory device.

公开(公告)号：US20240177747A1

公开(公告)日：2024-05-30

申请号：US18388680

申请日：2023-11-10

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F12/00 ,  G06F13/16

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US10593379B2

公开(公告)日：2020-03-17

申请号：US16109607

申请日：2018-08-22

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C8/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20190392875A1

公开(公告)日：2019-12-26

申请号：US16459330

申请日：2019-07-01

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G11C7/22 ,  G11C7/02 ,  G06F13/16

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

公开(公告)号：US10062421B2

公开(公告)日：2018-08-28

申请号：US15626097

申请日：2017-06-17

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C8/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20140140149A1

公开(公告)日：2014-05-22

申请号：US13959633

申请日：2013-08-05

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G11C7/22 ,  G11C7/02

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/02 ,  G11C7/22

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract translation: 存储器控制器包括用于接收数据选通信号和对应的读取数据的接口。 数据选通信号和读取数据对应于由存储器控制器发出的读取命令，并且根据数据选通信号和使能信号接收读取的数据。 存储器控制器中的电路是动态地调整使能信号和数据选通信号之间的定时偏移，并且控制逻辑将根据从自由信号发出的最后读取命令以来的时间间隔的确定发出补充读取命令 存储器控制器超过预定值。