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    Testing fuse configurations in semiconductor devices
    1.
    发明授权
    Testing fuse configurations in semiconductor devices 有权
    测试半导体器件中的保险丝配置

    公开(公告)号：US09568544B2

    公开(公告)日：2017-02-14

    申请号：US14250191

    申请日：2014-04-10

    Applicant: RAMBUS INC.

    Inventor： Adrian E. Ong ,  Paul Fuller ,  Nick van Heel ,  Mark Thomann

    IPC: G01R31/02 ,  G01R31/28 ,  G01R31/317

    CPC classification number: G01R31/31722 ,  G01R31/2851 ,  G01R31/31723 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2924/00012

    Abstract: A system includes a first integrated circuit configured to operate in at least a normal mode and a test mode and a second integrated circuit, where both the first integrated circuit and the second integrated circuit are disposed within a same semiconductor device package. The system further includes a first terminal, external to the semiconductor device package, electronically coupled to the first integrated circuit and the second integrated circuit. The first terminal is electronically coupled to a buffer in the second integrated circuit and used to convey signals to or from the first integrated circuit.

    Abstract translation: 一种系统包括被配置为在至少正常模式和测试模式下工作的第一集成电路和第二集成电路，其中第一集成电路和第二集成电路均设置在相同的半导体器件封装内。 该系统还包括电子耦合到第一集成电路和第二集成电路的半导体器件封装外部的第一端子。 第一端子电耦合到第二集成电路中的缓冲器，并用于将信号传送到第一集成电路或从第一集成电路传送信号。

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