公开(公告)号：US20220005804A1

公开(公告)日：2022-01-06

申请号：US17476099

申请日：2021-09-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Fujio SHIMIZU ,  Tsuyoshi KACHI ,  Yoshinori YOSHIDA

IPC: H01L27/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/06 ,  H01L21/762

Abstract: A semiconductor device with an insulated-gate field-effect transistor and its manufacturing method. The cell region EFR defined in the first region of one main surface side of semiconductor substrate (SUB), an insulated gate-type field-effect transistor (MFET) is formed, the gate pad region GPR defined in the first region, snubber circuit SNC is formed snubber region SNR is defined. Within the first and second regions, first and second deep trenches spaced apart from each other are formed, and at least one width of the plurality of second deep trenches formed in the second region is smaller than that of the first deep trench formed in the first region.

公开(公告)号：US20190043943A1

公开(公告)日：2019-02-07

申请号：US16019808

申请日：2018-06-27

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori YOSHIDA ,  Tsuyoshi KACHI

IPC: H01L29/06 ,  H01L23/00 ,  H01L21/225 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor substrate is easily warped by the shrink of the insulating film formed within the deep trench according to the thermal processing in the super junction structure. In order to solve the above problem, in a semiconductor device, an element region and a terminal region are defined on one main surface of the semiconductor substrate. The terminal region is arranged to surround the element region. In the terminal region, a plurality of buried insulators are formed from the main surface of the semiconductor substrate in a way of penetrating an n-type diffusion layer and an n-type column layer and arriving at an n-type epitaxial layer. The buried insulator is formed within a deep trench. The plural buried insulators are arranged in island shapes mutually at a distance from each other.

公开(公告)号：US20190131448A1

公开(公告)日：2019-05-02

申请号：US16116598

申请日：2018-08-29

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori YOSHIDA ,  Tsuyoshi KACHI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811

Abstract: Provided are a semiconductor device including a desired snubber part in accordance with use of the semiconductor device and a method of manufacturing the semiconductor device. A snubber region having a snubber part is defined in a gate pad region defined on a side close to a first main surface of a semiconductor substrate. A p-type diffusion layer and an n-type column layer contacted to each other are formed in the snubber region. The p-type diffusion layer and the n-type column layer are formed as a parasitic capacitance of the snubber part while the n-type column layer is electrically coupled to a drain. The p-type diffusion layer, which extends in a Y-axis direction, is a resistance of the snubber part and electrically coupled to a source.