公开(公告)号：US20190198660A1

公开(公告)日：2019-06-27

申请号：US16184602

申请日：2018-11-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tsuyoshi KACHI

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7808 ,  H01L29/0619 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/404 ,  H01L29/66734 ,  H01L29/7813

Abstract: There is provided a semiconductor device and its manufacturing method capable of avoiding generation of a through-current flowing between the drain and source and suppressing the potential fluctuation with time in the field plate electrode. A drain region is arranged on a first surface of a semiconductor substrate, a source region is arranged on a second surface thereof, and a drift region is arranged between the drain region and the source region. The semiconductor substrate has a trench extending from the second surface into the drift region. The field plate electrode is arranged within the trench to be electrically insulated from the drain region and insulated from the drift region oppositely. The Zener diode is electrically coupled between the source region and the field plate electrode. The Zener diode is coupled in a forward direction from the source region to the field plate electrode.

公开(公告)号：US20170229572A1

公开(公告)日：2017-08-10

申请号：US15428350

申请日：2017-02-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Senichirou NAGASE ,  Tsuyoshi KACHI ,  Yoshinori HOSHINO

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66734 ,  H01L29/7813

Abstract: To provide a semiconductor device equipped with a snubber portion having an improved withstand voltage and capable of reducing a surge voltage at turn-off of an insulated gate field effect transistor portion. The concentration of a first conductivity type impurity in a snubber semiconductor region is greater than that in a drift layer. The thickness of a snubber insulating film between the snubber semiconductor region and a snubber electrode is greater than that of a gate insulating film between a gate electrode and a body region.

公开(公告)号：US20140145260A1

公开(公告)日：2014-05-29

申请号：US14170430

申请日：2014-01-31

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi MATSUURA ,  Yoshito NAKAZAWA ,  Tsuyoshi KACHI ,  Yuji YATSUDA

IPC: H01L27/06 ,  H01L29/872 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

Abstract translation: 栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为 形成在突出部分的侧壁部分上。 形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

公开(公告)号：US20200321464A1

公开(公告)日：2020-10-08

申请号：US16827150

申请日：2020-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Senichirou NAGASE ,  Tsuyoshi KACHI ,  Yoshinori HOSHINO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/66

Abstract: In a deep trench DTC reaching a predetermined depth from a first main surface of a semiconductor substrate SUB, a plurality of columnar conductors CCB including plugs PUG and field plates FP are formed. A p type impurity layer PIL is formed along the side wall surface of the deep trench DTC. Between the bottom of the plug PUG and the bottom of the p type impurity layer PIL, the field plate FP and the p type impurity layer PIL are positioned to face each other via an insulating film FIF interposed therebetween. Between the bottom of the p type impurity layer PIL and the bottom of the field plate FP, the field plate FP and an n-type drift layer NDL of the semiconductor substrate SUB are positioned to face each other via the insulating film FIF interposed therebetween.

公开(公告)号：US20190131448A1

公开(公告)日：2019-05-02

申请号：US16116598

申请日：2018-08-29

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori YOSHIDA ,  Tsuyoshi KACHI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811

Abstract: Provided are a semiconductor device including a desired snubber part in accordance with use of the semiconductor device and a method of manufacturing the semiconductor device. A snubber region having a snubber part is defined in a gate pad region defined on a side close to a first main surface of a semiconductor substrate. A p-type diffusion layer and an n-type column layer contacted to each other are formed in the snubber region. The p-type diffusion layer and the n-type column layer are formed as a parasitic capacitance of the snubber part while the n-type column layer is electrically coupled to a drain. The p-type diffusion layer, which extends in a Y-axis direction, is a resistance of the snubber part and electrically coupled to a source.

公开(公告)号：US20160043206A1

公开(公告)日：2016-02-11

申请号：US14806115

申请日：2015-07-22

Applicant: Renesas Electronics Corporation

Inventor： Yuta IKEGAMI ,  Tsuyoshi KACHI

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66348 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/32105 ,  H01L21/76895 ,  H01L21/8222 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6634 ,  H01L29/7397

Abstract: An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.

Abstract translation: 在半导体器件的性能方面实现了改进。 在IGBT的n型基极用半导体基板的主表面上形成绝缘层。 在绝缘层的沟槽中，在半导体衬底上形成n型半导体层，并且在半导体层的两侧，通过栅极绝缘膜形成栅电极。 在半导体层的上部形成p型基极的p型半导体区域和n型发射极的n +型半导体区域。 在栅电极下方存在绝缘层的部分。 通过栅极绝缘膜与栅极电极的与半导体层相对的侧面相对的侧面与绝缘层相邻。

公开(公告)号：US20220005804A1

公开(公告)日：2022-01-06

申请号：US17476099

申请日：2021-09-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Fujio SHIMIZU ,  Tsuyoshi KACHI ,  Yoshinori YOSHIDA

IPC: H01L27/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/06 ,  H01L21/762

Abstract: A semiconductor device with an insulated-gate field-effect transistor and its manufacturing method. The cell region EFR defined in the first region of one main surface side of semiconductor substrate (SUB), an insulated gate-type field-effect transistor (MFET) is formed, the gate pad region GPR defined in the first region, snubber circuit SNC is formed snubber region SNR is defined. Within the first and second regions, first and second deep trenches spaced apart from each other are formed, and at least one width of the plurality of second deep trenches formed in the second region is smaller than that of the first deep trench formed in the first region.

公开(公告)号：US20190043943A1

公开(公告)日：2019-02-07

申请号：US16019808

申请日：2018-06-27

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori YOSHIDA ,  Tsuyoshi KACHI

IPC: H01L29/06 ,  H01L23/00 ,  H01L21/225 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor substrate is easily warped by the shrink of the insulating film formed within the deep trench according to the thermal processing in the super junction structure. In order to solve the above problem, in a semiconductor device, an element region and a terminal region are defined on one main surface of the semiconductor substrate. The terminal region is arranged to surround the element region. In the terminal region, a plurality of buried insulators are formed from the main surface of the semiconductor substrate in a way of penetrating an n-type diffusion layer and an n-type column layer and arriving at an n-type epitaxial layer. The buried insulator is formed within a deep trench. The plural buried insulators are arranged in island shapes mutually at a distance from each other.

公开(公告)号：US20180019160A1

公开(公告)日：2018-01-18

申请号：US15592241

申请日：2017-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi KACHI ,  Yoshinori HOSHINO ,  Senichirou NAGASE

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/265 ,  H01L29/15 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

Abstract: Provided are a semiconductor device and a manufacturing method therefor that can prevent the breakage of an element and in which the control of impurity amounts is less susceptible to variations in manufacturing processes. A semiconductor substrate has a front surface and includes hole portions extending from the front surface to an inside of the substrate. N-type regions are formed in the semiconductor substrate. At wall surfaces of the hole portions, p-type regions are formed to configure p-n junction with the n-type regions. Each of the p-type regions includes a low-concentration region and a high-concentration region formed at the wall surface of each hole portion. A width of the high-concentration region along the wall surface of the hole portion becomes smaller from the front surface toward a deeper position.

公开(公告)号：US20180358434A1

公开(公告)日：2018-12-13

申请号：US15950977

申请日：2018-04-11

Applicant: Renesas Electronics Corporation

Inventor： Senichirou NAGASE ,  Tsuyoshi KACHI ,  Yoshinori HOSHINO

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/872

Abstract: A deep trench which reaches a predetermined depth from one principal surface is formed in an element region of a semiconductor substrate. A TEOS oxide film and a polycrystalline silicon film are formed so as to fill the deep trench. In formation of a MOSFET and in formation of a protective insulating film on/over a surface of an element region by thermal oxidation, a silicon thermal oxide film grows, the TEOS oxide film contracts and the polycrystalline silicon film expands when oxidized and turning into a silicon oxide film, and thereby an embedded insulator is formed in the deep trench.