-
公开(公告)号：US20220302912A1
公开(公告)日：2022-09-22
申请号：US17681728
申请日：2022-02-26
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Yi-Kuang Chen , Ming-Jun Hsiao
Abstract: A BD type pulse width modulation (PWM) circuit is configured to convert a pair of complementary input signals to a pair of output PWM signals. The BD PWM circuit modulates a basic modulation signal according to the pair of input signals, to generate a basic PWM signal. The common mode levels of the pair of input signals and the basic modulation signal are the same. The BD PWM circuit modulates an offset modulation signal according to the pair of input signals to generate an offset PWM signal. The offset modulation signal and the basic modulation signal have a non-zero offset in between. The BD PWM circuit selects the offset PWM signal or a heavy load PWM signal as the pair of output PWM signals. The heavy load PWM signal is correlated with the basic PWM signal.
-
公开(公告)号：US12009823B2
公开(公告)日：2024-06-11
申请号：US18049611
申请日：2022-10-25
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Yi-Kuang Chen
Abstract: A pulse width modulation (PWM) method for converting an input signal into an output PWM signal includes the following steps: generating a first linear periodic wave and a second linear periodic wave which are triangle waves or sawtooth waves, wherein the amplitude of the first linear periodic wave is greater than the amplitude of the second linear periodic wave; determining whether the level of the input signal is lower than a light load threshold; when the level of the input signal is lower than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the second linear periodic wave; and when the level of the input signal is higher than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the first linear periodic wave.
-
公开(公告)号：US12107586B2
公开(公告)日：2024-10-01
申请号：US17681728
申请日：2022-02-26
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Yi-Kuang Chen , Ming-Jun Hsiao
CPC classification number: H03K7/08 , H03F3/217 , H03F2200/351 , H03K3/017
Abstract: A BD type pulse width modulation (PWM) circuit is configured to convert a pair of complementary input signals to a pair of output PWM signals. The BD PWM circuit modulates a basic modulation signal according to the pair of input signals, to generate a basic PWM signal. The common mode levels of the pair of input signals and the basic modulation signal are the same. The BD PWM circuit modulates an offset modulation signal according to the pair of input signals to generate an offset PWM signal. The offset modulation signal and the basic modulation signal have a non-zero offset in between. The BD PWM circuit selects the offset PWM signal or a heavy load PWM signal as the pair of output PWM signals. The heavy load PWM signal is correlated with the basic PWM signal.
-
公开(公告)号：US11870400B2
公开(公告)日：2024-01-09
申请号：US17676594
申请日：2022-02-21
Applicant: Richtek Technology Corporation
Inventor： Yi-Kuang Chen
CPC classification number: H03F1/26 , H03F1/0216 , H03F3/217 , H03F2200/372
Abstract: A class-D amplifying system includes: a first digital-to-analog converter (DAC), a class-D amplifier circuit and a second DAC. The first DAC generates an analog input signal according to a digital input signal. The class-D amplifier circuit generates an output signal according to the analog input signal in a pulse width modulation (PWM) manner. The second DAC generates a common mode (CM) adjustment current for adjusting a CM voltage of the analog input signal according to one or more of the following parameters: (1) the CM voltage of the analog input signal; and/or (2) a driving power. A power stage circuit of the class-D amplifier circuit is powered by the driving power. The second DAC determines which parameter the CM adjustment current is correlated to according to: (A) A level state of the output signal; and/or (B) A level state of a PWM signal of the class-D amplifier circuit.
-
公开(公告)号：US20240128933A1
公开(公告)日：2024-04-18
申请号：US18468727
申请日：2023-09-17
Applicant: Richtek Technology Corporation
Inventor： Yi-Kuang Chen
CPC classification number: H03F1/0233 , H03F3/2173 , H03F2200/351
Abstract: A class-D amplifier circuit includes an amplifier circuit, a PWM circuit, a power stage circuit, a pair of feedback circuits, and a common-mode control circuit. The amplifier circuit receives a differential input signal at differential input ends to generate a differential intermediate signal. The PWM circuit generates a PWM signal according to the differential intermediate signal. The power stage circuit generates a differential output signal at differential output ends according to the PWM signal. The common-mode control circuit controls first and second high bandwidth transconductance circuits according to the output common-mode voltage of the differential output signal, so as to generate first and second common-mode control currents, thereby providing a common-mode control signal at the differential input ends to regulate the input common-mode voltage of the differential input signal at a predetermined input common-mode level.
-
Patent Agency Ranking
公开(公告)号：US11152927B1
公开(公告)日：2021-10-19
申请号：US17188962
申请日：2021-03-01
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Yi-Kuang Chen , Ming-Jun Hsiao
Abstract: A low distortion triangular wave generator circuit generates a triangular wave signal by performing integration on an integration capacitor via a charging current and a discharging current during a charging period and a discharging period within a switching period of an external clock signal. A time length of the charging period is identical to a time length of the discharging period. A common mode related signal related to a common mode characteristic of the triangular wave signal is generated. An adjusting signal is generated according to a difference between the common mode related signal and a predetermined DC (direct current) level. The adjusting signal adjusts at least one of the charging current and the discharging current via feedback mechanism such that the triangular wave signal is a symmetrical triangular wave, and an average voltage of the triangular wave signal is equal to a target DC level.
-
公开(公告)号：US20210305973A1
公开(公告)日：2021-09-30
申请号：US17188962
申请日：2021-03-01
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Yi-Kuang Chen , Ming-Jun Hsiao
Abstract: A low distortion triangular wave generator circuit generates a triangular wave signal by performing integration on an integration capacitor via a charging current and a discharging current during a charging period and a discharging period within a switching period of an external clock signal. A time length of the charging period is identical to a time length of the discharging period. A common mode related signal related to a common mode characteristic of the triangular wave signal is generated. An adjusting signal is generated according to a difference between the common mode related signal and a predetermined DC (direct current) level. The adjusting signal adjusts at least one of the charging current and the discharging current via feedback mechanism such that the triangular wave signal is a symmetrical triangular wave, and an average voltage of the triangular wave signal is equal to a target DC level.
-
8.发明公开公开(公告)号：US20240146295A1
公开(公告)日：2024-05-02
申请号：US18487997
申请日：2023-10-16
Applicant: Richtek Technology Corporation
Inventor： Yi-Kuang Chen
CPC classification number: H03K17/162 , H02M1/088 , H02M1/44 , H03K2217/0063 , H03K2217/0072
Abstract: A half-bridge driver drives a half-bridge circuit. The half-bridge driver includes a switch selection circuit and at least one slew rate adjustment circuit, wherein the slew rate adjustment circuit includes a pulse-width control unit, an adjustment pulling unit and a halt adjustment pulling unit. The switch selection circuit generates a source current or a sink current to correspondingly pull up or pull down the gate-source voltage of the upper switch or the lower switch, thereby turning-on or turning-off the upper switch or the lower switch. The adjustment pulling unit is for adjusting the pulling-up or pulling-down of the gate-source voltage of the upper switch or the lower switch. The stop-adjustment pulling unit is for stopping adjusting the pulling-up or pulling-down of the gate-source voltage of the upper switch or the lower switch.
-
公开(公告)号：US20230188120A1
公开(公告)日：2023-06-15
申请号：US18049611
申请日：2022-10-25
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Yi-Kuang Chen
Abstract: A pulse width modulation (PWM) method for converting an input signal into an output PWM signal includes the following steps: generating a first linear periodic wave and a second linear periodic wave which are triangle waves or sawtooth waves, wherein the amplitude of the first linear periodic wave is greater than the amplitude of the second linear periodic wave; determining whether the level of the input signal is lower than a light load threshold; when the level of the input signal is lower than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the second linear periodic wave; and when the level of the input signal is higher than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the first linear periodic wave.
-
公开(公告)号：US20220294396A1
公开(公告)日：2022-09-15
申请号：US17676594
申请日：2022-02-21
Applicant: Richtek Technology Corporation
Inventor： Yi-Kuang Chen
Abstract: A class-D amplifying system includes: a first digital-to-analog converter (DAC), a class-D amplifier circuit and a second DAC. The first DAC generates an analog input signal according to a digital input signal. The class-D amplifier circuit generates an output signal according to the analog input signal in a pulse width modulation (PWM) manner. The second DAC generates a common mode (CM) adjustment current for adjusting a CM voltage of the analog input signal according to one or more of the following parameters: (1) the CM voltage of the analog input signal; and/or (2) a driving power. A power stage circuit of the class-D amplifier circuit is powered by the driving power. The second DAC determines which parameter the CM adjustment current is correlated to according to: (A) A level state of the output signal; and/or (B) A level state of a PWM signal of the class-D amplifier circuit.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.018 seconds)
