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    Methods and circuits for decision-feedback equalization with early high-order-symbol detection
    1.
    发明授权
    Methods and circuits for decision-feedback equalization with early high-order-symbol detection 有权

    公开(公告)号：US11770275B2

    公开(公告)日：2023-09-26

    申请号：US17852278

    申请日：2022-06-28

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Nhat Nguyen ,  Charles Walter Boecker

    IPC: H04L25/03

    CPC classification number: H04L25/03057

    Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.

    Serial-link receiver using time-interleaved discrete time gain
    2.
    发明授权
    Serial-link receiver using time-interleaved discrete time gain 有权

    公开(公告)号：US11128499B2

    公开(公告)日：2021-09-21

    申请号：US17045769

    申请日：2019-03-25

    Applicant: Rambus Inc.

    Inventor： Haidang Lin ,  Charles Walter Boecker ,  Masum Hossain

    IPC: H03K5/15 ,  H04L25/03 ,  H04L25/49

    Abstract: A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.

    Symbol-Rate Phase Detector for Multi-PAM Receiver
    5.
    发明申请
    Symbol-Rate Phase Detector for Multi-PAM Receiver 有权

    公开(公告)号：US20210344529A1

    公开(公告)日：2021-11-04

    申请号：US17323271

    申请日：2021-05-18

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Nhat Nguyen ,  Charles Walter Boecker

    IPC: H04L25/49 ,  H04L25/03 ,  H04L7/00 ,  H04L7/033

    Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

    Symbol-Rate Phase Detector for Multi-PAM Receiver
    6.
    发明申请
    Symbol-Rate Phase Detector for Multi-PAM Receiver 审中-公开

    公开(公告)号：US20200313938A1

    公开(公告)日：2020-10-01

    申请号：US16847793

    申请日：2020-04-14

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Nhat Nguyen ,  Charles Walter Boecker

    IPC: H04L25/49 ,  H04L7/00 ,  H04L7/033 ,  H04L25/03

    Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

    Symbol-Rate Phase Detector for Multi-PAM Receiver
    7.
    发明申请
    Symbol-Rate Phase Detector for Multi-PAM Receiver 审中-公开

    公开(公告)号：US20200007363A1

    公开(公告)日：2020-01-02

    申请号：US16455479

    申请日：2019-06-27

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Nhat Nguyen ,  Charles Walter Boecker

    IPC: H04L25/49 ,  H04L25/03 ,  H04L7/033 ,  H04L7/00

    Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

    Methods and Circuits for Decision-Feedback Equalization with Early High-Order-Symbol Detection
    8.
    发明申请
    Methods and Circuits for Decision-Feedback Equalization with Early High-Order-Symbol Detection 有权

    公开(公告)号：US20220407749A1

    公开(公告)日：2022-12-22

    申请号：US17852278

    申请日：2022-06-28

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Nhat Nguyen ,  Charles Walter Boecker

    IPC: H04L25/03

    Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.

    Adjustment of multi-phase clock system
    9.
    发明授权
    Adjustment of multi-phase clock system 有权

    公开(公告)号：US11283435B2

    公开(公告)日：2022-03-22

    申请号：US16721116

    申请日：2019-12-19

    Applicant: Rambus Inc.

    Inventor： Charles Walter Boecker ,  Roxanne Vu ,  Eric Douglas Groen

    IPC: H03K5/13 ,  H03K5/135 ,  H03K3/356 ,  H03K5/00

    Abstract: Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.

    Direct-Switching H-Bridge Current-Mode Drivers
    10.
    发明申请
    Direct-Switching H-Bridge Current-Mode Drivers 有权

    公开(公告)号：US20210305956A1

    公开(公告)日：2021-09-30

    申请号：US17270223

    申请日：2019-07-22

    Applicant: Rambus Inc.

    Inventor： Eric Douglas Groen ,  Charles Walter Boecker

    IPC: H03F3/45 ,  H03F3/26 ,  H04L25/49

    Abstract: A current-mode transmitter amplifies a differential input signal to a differential, current-mode output signal. A split-input, current-mode-logic stage produces small, analog signals to limit switching currents and thus power consumption and power-supply noise. These small, analog signals are driven through a source-follower stage to reduce loading and shift the common-mode voltage to a desired level. A switched-current-source H-bridge driver combines differential outputs from the source-follower stage to provide an amplified differential output current. The output swing from the H-bridge driver is controlled by the voltage level from the source follower and derived from a replica-bias structure.

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