公开(公告)号：US20160028323A1

公开(公告)日：2016-01-28

申请号：US14874240

申请日：2015-10-02

Applicant: Renesas Electronics Corporation

Inventor： Yoichi YOSHIDA

IPC: H02M7/217 ,  H01L27/06

CPC classification number: H02M7/217 ,  H01L27/0629 ,  H02M7/02 ,  H02M7/103 ,  H02M2001/0048 ,  H02M2007/2195 ,  Y02B70/1408 ,  Y02B70/1491 ,  Y10T307/25

Abstract: A semiconductor device comprising a rectifier circuit, wherein the rectifier circuit includes first and second input wires to which AC signals whose phases are inverted from each other are transmitted; a first transistor of a first conductive type which has a first power wire connected with a first transistor terminal and a gate connected with the first input wire; a second transistor of the first conductive type which has the first power wire connected with a first transistor terminal, and a gate connected with the second input wire; a third transistor of a second conductive type which has a second power wire connected with a first transistor terminal, a second transistor terminal connected with a second transistor terminal of the first transistor and a gate connected with the first input capacitor; and a fourth transistor of the second conductive type which has the second power wire connected with a first transistor terminal.

Abstract translation: 一种包括整流电路的半导体器件，其中整流器电路包括第一和第二输入引线，相互相互反相的AC信号被发送到该第一和第二输入引线; 第一导电类型的第一晶体管，其具有与第一晶体管端子连接的第一电源线和与第一输入线连接的栅极; 第一导电类型的第二晶体管，其具有与第一晶体管端子连接的第一电源线，以及与第二输入线连接的栅极; 具有与第一晶体管端子连接的第二电源线的第二导电类型的第三晶体管，与第一晶体管的第二晶体管端子连接的第二晶体管端子和与第一输入电容器连接的栅极; 以及具有与第一晶体管端子连接的第二电源线的第二导电类型的第四晶体管。

公开(公告)号：US20150311706A1

公开(公告)日：2015-10-29

申请号：US14690381

申请日：2015-04-18

Applicant: Renesas Electronics Corporation

Inventor： Koichiro NOGUCHI ,  Koichi NOSE ,  Yoshifumi IKENAGA ,  Yoichi YOSHIDA

IPC: H02J1/04 ,  H02M7/06

CPC classification number: H02J50/20 ,  H02J1/102 ,  H02J7/025 ,  H02J17/00 ,  H02J50/40

Abstract: A power supply device according to an embodiment comprises a plurality of power sources 10 each including an antenna and an AC/DC conversion unit, a plurality of consolidating units 13—1 to 13—i, and a power supply unit 15. The consolidating units 13—1 to 13—i respectively include consolidating circuits 14—1 to 14—i that selectively consolidate a plurality of DC signals 21—1 to 21—n supplied by the plurality of power sources 10. The power supply unit 15 includes a consolidating circuit 16 that selectively consolidates the DC signals 21—1 to 21—i output from the plurality of consolidating units 13—1 to 13—i, and a voltage conversion circuit 17 that converts a DC signal 23 resulting from consolidation in the consolidating circuit 16, to a predetermined voltage.

Abstract translation: 根据实施例的电源装置包括多个电源10，每个电源10包括天线和AC / DC转换单元，多个合并单元13-1至13-i和电源单元15.合并单元 13-1至13-i分别包括选择性地合并由多个电源10提供的多个DC信号21-1至21-n的合并电路14-1至14-i。电源单元15包括合并 电路16，其选择性地合并从多个合并单元13-1至13-i输出的DC信号21-1至21-i;以及电压转换电路17，其将由巩固电路16中的合并产生的DC信号23转换 ，达到预定电压。

公开(公告)号：US20160065070A1

公开(公告)日：2016-03-03

申请号：US14823579

申请日：2015-08-11

Applicant: Renesas Electronics Corporation

Inventor： Koichiro NOGUCHI ,  Koichi NOSE ,  Yoshifumi IKENAGA ,  Yoichi YOSHIDA

IPC: H02M3/158

CPC classification number: H03K17/162 ,  H02M1/36 ,  H02M3/07 ,  H02M3/155 ,  H03K17/0814

Abstract: According to one embodiment, a semiconductor device includes: a first switch SWx which switches whether or not to supply a first power supply voltage Vx generated by accumulating a charge outputted from a power source 10, as a second power supply voltage VDD to a first circuit 13, and a second switch SW1 which switches whether or not to connect to the first circuit 13 a smoothing capacitor C1 which suppresses a fluctuation of the second power supply voltage VDD, and the first switch SWx is switched to an on state in response to that the first power supply voltage Vx has reached a sufficient voltage, and then the second switch SW1 is switched to the on state in response to that the second power supply voltage VDD has reached a sufficient voltage.

Abstract translation: 根据一个实施例，半导体器件包括：第一开关SWx，其切换是否将通过累积从电源10输出的电荷产生的第一电源电压Vx作为第二电源电压VDD提供给第一电路 13以及第二开关SW1，其切换是否连接到第一电路13的平滑电容器C1，其抑制第二电源电压VDD的波动，并且响应于该第一开关SWx将第一开关SWx切换到导通状态 第一电源电压Vx已经达到足够的电压，然后响应于第二电源电压VDD达到足够的电压而将第二开关SW1切换到导通状态。

公开(公告)号：US20180083494A1

公开(公告)日：2018-03-22

申请号：US15826062

申请日：2017-11-29

Applicant: Renesas Electronics Corporation

Inventor： Koichiro NOGUCHI ,  Koichi NOSE ,  Yoshifumi IKENAGA ,  Yoichi YOSHIDA

IPC: H02J50/20 ,  H02J7/02 ,  H02J50/40 ,  H02J1/10

CPC classification number: H02J50/20 ,  H02J1/102 ,  H02J7/025 ,  H02J17/00 ,  H02J50/40

Abstract: A power supply device includes a plurality of power sources each including an antenna and an AC/DC conversion unit that converts an AC signal received by the antenna to a DC signal, a plurality of consolidating units each including a first consolidating circuit that selectively consolidates a plurality of DC signals supplied by the plurality of power sources, and a power supply unit that includes a second consolidating circuit that selectively consolidates DC signals output from the plurality of consolidating units, and a first voltage conversion circuit that converts a DC signal resulting from consolidation in the second consolidating circuit, to a predetermined voltage.

公开(公告)号：US20180323779A1

公开(公告)日：2018-11-08

申请号：US16024097

申请日：2018-06-29

Applicant: Renesas Electronics Corporation

Inventor： Koichiro NOGUCHI ,  Koichi NOSE ,  Yoshifumi IKENAGA ,  Yoichi YOSHIDA

IPC: H03K17/16

CPC classification number: H03K17/162 ,  H02M1/36 ,  H02M3/07 ,  H02M3/155 ,  H03K17/0814

Abstract: According to one embodiment, a semiconductor device includes: a first switch SWx which switches whether or not to supply a first power supply voltage Vx generated by accumulating a charge outputted from a power source 10, as a second power supply voltage VDD to a first circuit 13, and a second switch SW1 which switches whether or not to connect to the first circuit 13 a smoothing capacitor C1 which suppresses a fluctuation of the second power supply voltage VDD, and the first switch SWx is switched to an on state in response to that the first power supply voltage Vx has reached a sufficient voltage, and then the second switch SW1 is switched to the on state in response to that the second power supply voltage VDD has reached a sufficient voltage.

公开(公告)号：US20160140077A1

公开(公告)日：2016-05-19

申请号：US14919961

申请日：2015-10-22

Applicant: Renesas Electronics Corporation

Inventor： Yoichi YOSHIDA

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/362

CPC classification number: G06F13/4282 ,  G06F13/362 ,  G06F13/4068 ,  G06F2213/0016

Abstract: To provide a serial communication system that can flexibly or easily change a system configuration. For example, when coupled to first and second serial buses, a motor module transmits a first signal to the second serial bus. Subsequently, the motor module transmits a first command containing a candidate address to the first serial bus; meanwhile, the motor module searches for an address where an acknowledgement is not received in response to the first command. The motor module transmits the search result address to the second serial bus. A control unit at the reception of the first signal changes to a sleep state that stops communications with the first serial bus and receives an address as a search result from the second serial bus.

Abstract translation: 提供可以灵活或轻松地更改系统配置的串行通信系统。 例如，当耦合到第一和第二串行总线时，电机模块将第一信号发送到第二串行总线。 随后，电机模块向第一串行总线发送包含候选地址的第一命令; 同时，电机模块响应于第一命令搜索未接收到确认的地址。 电机模块将搜索结果地址发送到第二串行总线。 接收到第一信号时的控制单元变为休眠状态，停止与第一串行总线的通信，并从第二串行总线接收作为搜索结果的地址。

公开(公告)号：US20150280606A1

公开(公告)日：2015-10-01

申请号：US14534105

申请日：2014-11-05

Applicant: Renesas Electronics Corporation

Inventor： Yoichi YOSHIDA

IPC: H02M7/217 ,  H01L27/06

CPC classification number: H02M7/217 ,  H01L27/0629 ,  H02M7/02 ,  H02M7/103 ,  H02M2001/0048 ,  H02M2007/2195 ,  Y02B70/1408 ,  Y02B70/1491 ,  Y10T307/25

Abstract: A semiconductor device according to one embodiment includes first and second transistor columns which each include a NMOS transistor and a PMOS transistor which are connected in series between a first power wire and a second power wire. Further, a gate of the PMOS transistor of one transistor column is connected to a wire which connects the NMOS transistor and the PMOS transistor of the other transistor column. Furthermore, an AC signal obtained by superimposing a signal on a bias voltage which is a voltage lower than that of the gate of the PMOS transistor included in the same transistor column is supplied to the gate of the NMOS transistor included in the transistor column.

Abstract translation: 根据一个实施例的半导体器件包括第一和第二晶体管列，每个晶体管列包括串联连接在第一电源线和第二电源线之间的NMOS晶体管和PMOS晶体管。 此外，一个晶体管列的PMOS晶体管的栅极连接到连接另一个晶体管列的NMOS晶体管和PMOS晶体管的导线。 此外，通过将包含在同一晶体管列中的PMOS晶体管的栅极的电压比作为低电压的偏置电压叠加的AC信号提供给晶体管列的NMOS晶体管的栅极。