公开(公告)号：US5424492A

公开(公告)日：1995-06-13

申请号：US178078

申请日：1994-01-06

申请人： Robert B. Petty ,  Michael D. Ohlinger ,  Deepak N. Swamy ,  Joseph Mallory

发明人： Robert B. Petty ,  Michael D. Ohlinger ,  Deepak N. Swamy ,  Joseph Mallory

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K1/00

CPC分类号： H05K1/115 ,  H05K1/114 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2924/01039 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/09227 ,  H05K2201/10734

摘要： An optimal routing methodology for routing high I/O density packages which minimizes the number of PCB layers required. One feature of this routing methodology comprises treating respective I/O that are routed at the top layer of the package as surface mount technology (SMT) pads without dropping vias within the BGA grid, as is commonplace in the industry. This facilitates the use of fewer escapes and allows for more efficient use of the available space. Signal lines on the top layer of the package which must be routed to other layers of the PCB are connected to vias outside of the area of local high signal density on the printed circuit board. The placement of vias outside the area of local high density, i.e., in a depopulated area, reduces the number of layers necessary in the PCB to properly route the signals. This placement also facilitates the use of filtering capacitors to meet EMI requirements. In addition, all voltage pins are placed on the innermost or outermost grids and have clearanced vias. The device is also preferably placed at the beginning or at the end of the bus to maximize the routing efficiency.

摘要翻译： 用于布线高I / O密度封装的最佳路由方法，其最小化所需的PCB层数量。 该路由选择方法的一个特征包括处理作为表面贴装技术（SMT）焊盘而在封装顶层布线的相应I / O，而不会在BGA网格内掉下通孔，这在工业中是常见的。 这有助于使用更少的转义，并允许更有效地使用可用空间。 封装顶层上必须连接到PCB其他层的信号线连接到印刷电路板上局部高信号密度区域之外的通孔。 在局部高密度区域（即，在人口稀少的区域）之外的通孔的放置减少了PCB中所需的层数以适当地路由信号。 该放置还有助于使用滤波电容器来满足EMI要求。 此外，所有电压引脚都放置在最内侧或最外侧的栅格上，并具有通孔。 该装置还优选地放置在总线的开始或结束处以最大化路由效率。