公开(公告)号：US20240341037A1

公开(公告)日：2024-10-10

申请号：US18747008

申请日：2024-06-18

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Pierino CALASCIBETTA

IPC: H05K1/18 ,  H01Q1/22 ,  H01Q9/16 ,  H05K1/11

CPC classification number: H05K1/184 ,  H01Q1/22 ,  H01Q9/16 ,  H05K1/115 ,  H05K1/183 ,  H05K2201/10098 ,  H05K2201/10734

Abstract: A base substrate has a thickness between two faces. The base substrate includes at least one hole extending in a thickness of the base substrate perpendicular to one of the two face. At least one dipole of a surface-mount device type is housed in the at least one hole of the base substrate.

公开(公告)号：US20240334608A1

公开(公告)日：2024-10-03

申请号：US18740889

申请日：2024-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei HSU ,  Ming-Chih YEW ,  Po-Chen LAI ,  Po-Yao LIN ,  Shin-Puu JENG

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K3/28 ,  H05K3/34

CPC classification number: H05K1/181 ,  H01L25/0655 ,  H05K3/284 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/95001 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10727 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/107

Abstract: A method for forming a semiconductor package is provided. The method includes mounting a semiconductor device on a surface of a package substrate. The method also includes forming an underfill element between the semiconductor device and the surface of the package substrate. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The method also includes forming one or more grooves in the fillet portion.

公开(公告)号：US12089357B2

公开(公告)日：2024-09-10

申请号：US17958540

申请日：2022-10-03

Applicant: TE Connectivity Solutions GmbH

Inventor： Christopher William Blackburn ,  Jeffery Walter Mason ,  Nathan Lincoln Tracy ,  Clarence Leon Yu ,  Michael David Herring

IPC: H05K7/10 ,  H01R12/70 ,  H01R12/71

CPC classification number: H05K7/1084 ,  H01R12/7076 ,  H01R12/714 ,  H05K7/1069 ,  H05K7/1092 ,  H05K2201/10189 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/2018

Abstract: An electronic assembly includes an electronic package connected to a host circuit board. The electronic assembly includes interposer assemblies electrically connected to the electronic package. The electronic assembly includes cable modules coupled to upper separable interface of the interposer assemblies. The electronic assembly includes carrier assemblies configured to be coupled to an upper surface of the electronic package. Each carrier assembly includes a carrier base block and a carrier lid configured to hold at least one interposer assembly and at least one cable module. The carrier assemblies hold the cable modules with the module contacts in electrical connection with upper mating interfaces of the interposer contacts. The carrier assemblies hold lower mating interfaces of the interposer contacts in electrical connection with upper package contacts of the electronic package. The carrier assemblies are separately removable from the electronic package to separate the interposer assemblies from the electronic package.

公开(公告)号：US12030138B2

公开(公告)日：2024-07-09

申请号：US17642617

申请日：2020-09-11

Applicant: LIFCO INDUSTRIE

Inventor： Constantin Iacob ,  Sébastien Bucher

IPC: B23K35/02 ,  B23K35/30 ,  H05K1/02 ,  H05K3/34

CPC classification number: B23K35/0222 ,  B23K35/3006 ,  B23K35/302 ,  B23K35/3033 ,  H05K1/0271 ,  H05K3/3436 ,  H05K3/3473 ,  H05K2201/10734 ,  H05K2203/0435

Abstract: The present invention relates to a method for manufacturing composite solder balls that are metallized on the surface and calibrated, these balls comprising a core consisting of a spherical support particle of diameter D0 made of expanded polystyrene and having an intergranular porosity of at least 50%, and a shell covering said support particle and formed by a plurality of metallic surface layers. The present invention also relates to balls that can be obtained by the method according to the invention, as well as to the use thereof for the assembly of electronic boards.

公开(公告)号：US12022619B2

公开(公告)日：2024-06-25

申请号：US18309413

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyun Seok ,  Gyu Chae Lee ,  Jeong Hyeon Cho

IPC: H05K1/18 ,  H01L25/18 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L25/18 ,  H05K1/117 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal receive the first signal from the buffer at the same time. The first connection terminal is closer to the buffer as compared with the second connection terminal. The third connection terminal is closer to the buffer as compared with the fourth connection terminal.

公开(公告)号：US20240194390A1

公开(公告)日：2024-06-13

申请号：US18444674

申请日：2024-02-17

Applicant: Delta Electronics, Inc.

Inventor： Yahong Xiong ,  Da Jin ,  Qinghua Su

IPC: H01F27/28 ,  G05F1/575 ,  G06F1/18 ,  H01F17/04 ,  H01F17/06 ,  H01F27/02 ,  H01F27/24 ,  H01F27/29 ,  H01L25/16 ,  H01R12/52 ,  H01R12/58 ,  H02M3/00 ,  H02M3/158 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/28 ,  H05K7/14 ,  H05K7/20

CPC classification number: H01F27/2804 ,  G05F1/575 ,  G06F1/183 ,  H01F17/04 ,  H01F17/06 ,  H01F27/02 ,  H01F27/24 ,  H01F27/292 ,  H01L25/16 ,  H01R12/52 ,  H01R12/58 ,  H02M3/003 ,  H02M3/1584 ,  H05K1/0203 ,  H05K1/111 ,  H05K1/117 ,  H05K1/145 ,  H05K1/165 ,  H05K1/181 ,  H05K1/186 ,  H05K3/284 ,  H05K7/1427 ,  H05K7/2089 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10053 ,  H05K2201/10166 ,  H05K2201/10522 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2201/10984

Abstract: An apparatus includes a heat-dissipating substrate, a power circuit and a magnetic assembly. The heat-dissipating substrate includes a thermal contact surface. The power circuit includes at least one switch element in contact with the thermal contact surface of the heat-dissipating substrate. The magnetic assembly includes at least one first electrical conductor and a magnetic core module comprising at least one hole, wherein the at least one first electrical conductor passes through the at least one hole, and a terminal of the at least one first electrical conductor is electrically connected to the at least one switch element. The heat-dissipating substrate, the power circuit and the magnetic assembly are arranged in sequence along a same direction. A projection of the power circuit on the thermal contact surface partially overlaps a projection of the magnetic assembly on the thermal contact surface.

公开(公告)号：US20240172364A1

公开(公告)日：2024-05-23

申请号：US18284781

申请日：2023-01-06

Applicant: Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Fan LI

IPC: H05K1/14 ,  H05K1/02 ,  H05K1/11 ,  H10K59/131 ,  H10K59/40

CPC classification number: H05K1/144 ,  H05K1/028 ,  H05K1/115 ,  H10K59/131 ,  H10K59/40 ,  H05K2201/10128 ,  H05K2201/10734

Abstract: Disclosed is a circuit board, including: a first circuit board, a second circuit board and a conductive portion. The first circuit board includes a first substrate, a wire group and a substrate connection pad. A first wire group includes a first wire and a second wire disposed on two sides of the first substrate. A first substrate connection pad is electrically connected to the second wire via a via hole. The second circuit board includes a second substrate, a wire and a relay connection pad, wherein the wire and the relay connection pad are disposed on the second substrate. One end of the wire is electrically connected to a first relay connection pad.

公开(公告)号：US20240147624A1

公开(公告)日：2024-05-02

申请号：US18498080

申请日：2023-10-31

Applicant: CANON KABUSHIKI KAISHA

Inventor： NORITAKE TSUBOI

IPC: H05K1/18 ,  H01L25/16 ,  H05K3/34

CPC classification number: H05K1/181 ,  H01L25/16 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/3485 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2203/0465

Abstract: An electronic module includes a first wiring component, a first electronic component, a first bonding member, and a second bonding member. The first wiring component includes a first pad, a second pad, and a first insulating member. The first pad, the second pad, and the first insulating member are formed in a first mounting surface. The first electronic component includes a first electrode and a second electrode and is surface-mounted on the first mounting surface. The first bonding member is configured to bond the first pad and the first electrode together. The second bonding member is configured to bond the second pad and the second electrode together. The first electrode and the second electrode are positioned on an insulating area of the first mounting surface. A distance between the first electrode and the first insulating member is smaller than a distance between the first electrode and the first pad.

公开(公告)号：US11963311B2

公开(公告)日：2024-04-16

申请号：US17704303

申请日：2022-03-25

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Woong Choi ,  Yun Je Ji ,  Seung Eun Lee ,  Yong Hoon Kim

IPC: H05K1/11 ,  H01L23/498 ,  H05K1/18 ,  H05K3/34 ,  H05K3/46

CPC classification number: H05K3/4697 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/115 ,  H05K1/182 ,  H05K1/183 ,  H05K3/34 ,  H05K3/4644 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10734

Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers and having a cavity penetrating through a portion of the plurality of insulating layers, a passive component disposed in the cavity and including an external electrode electrically connected to at least one of the plurality of wiring layers, and a bridge disposed on the passive component in the cavity and including one or more circuit layers electrically connected to the external electrode.

公开(公告)号：US20240107665A1

公开(公告)日：2024-03-28

申请号：US17934651

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Biancun Xie ,  Shree Krishna Pandey ,  Chin-Kwan Kim ,  Ryan Lane ,  Charles David Paynter

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K3/4644 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/10015 ,  H05K2201/10734

Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.