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    High-performance capacitor packaging for next generation power electronics
    3.
    发明授权
    High-performance capacitor packaging for next generation power electronics 有权

    公开(公告)号：US12100560B2

    公开(公告)日：2024-09-24

    申请号：US17742690

    申请日：2022-05-12

    Applicant: UT-Battelle, LLC

    Inventor： Shajjad Chowdhury ,  Raj Sahu ,  Emre Gurpinar ,  Burak Ozpineci

    IPC: H01G4/38 ,  H01G4/232 ,  H05K1/16 ,  H01G4/12

    CPC classification number: H01G4/38 ,  H01G4/232 ,  H05K1/162 ,  H01G4/1245 ,  H05K2201/09227

    Abstract: A capacitor packaging having a central termination and three or more capacitors (or groups of capacitors) arranged about the central termination. The electrical flow paths between the termination and the capacitors or groups of capacitors are of substantially the same length. The capacitors or groups of capacitors may be arranged in a generally circular pattern with the termination centered on the center. The termination may include first and second terminals. The capacitors may be mounted to a printed circuit board (“PCB”) with traces on opposite surfaces of the PCB providing electrical flow paths from the terminals to opposite legs of the capacitors. The capacitor packaging may include a primary PCB with a first circular arrangement of capacitors and a secondary PCB with a second circular arrangement of capacitors. The capacitors may be sandwiched between the PCBs with the second arrangement of capacitors disposed concentrically inwardly of the first arrangement.

    ELECTRONIC CIRCUIT AND CORRESPONDING PROTECTION METHOD
    5.
    发明公开
    ELECTRONIC CIRCUIT AND CORRESPONDING PROTECTION METHOD 审中-公开

    公开(公告)号：US20240260176A1

    公开(公告)日：2024-08-01

    申请号：US18425339

    申请日：2024-01-29

    Applicant: BULL SAS

    Inventor： Sylvain DUCLOYER ,  Nicolas COULON ,  Yannick DOUARD

    IPC: H05K1/02 ,  H05K1/18

    CPC classification number: H05K1/0292 ,  H05K1/181 ,  H05K2201/09227

    Abstract: The invention relates to an electronic circuit comprising a substrate and at least one electronic component (3, 6),



    each electronic component (3, 6) including at least one data port (12) for receiving data,
    the electronic circuit (2) further comprising, for each data port (12):
    a current injection terminal (8);
    a breakable electrical trace (10) located in the thickness of the substrate and extending between the data port (12) and the injection terminal (8),
    each breakable electrical trace (10) comprising a fusible segment (20) and being configured to break, by melting of the fusible segment (20), upon the injection, at the injection terminal (8), of an electric current (I) having an intensity greater than a predetermined trace breaking threshold.

    WIRING SUBSTRATE
    6.
    发明公开
    WIRING SUBSTRATE 审中-公开

    公开(公告)号：US20240113008A1

    公开(公告)日：2024-04-04

    申请号：US18263163

    申请日：2021-12-20

    Applicant: Niterra Co., Ltd.

    Inventor： Kensuke MATSUHASHI

    IPC: H01L23/498 ,  H01L23/13 ,  H01L23/14 ,  H01L23/15 ,  H05K1/11

    CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/142 ,  H01L23/15 ,  H05K1/11 ,  H05K2201/09227

    Abstract: A wiring substrate includes a first ceramic layer and a second ceramic layer. A plurality of wiring traces which are electrically independent of one another are provided between the first ceramic layer and the second ceramic layer. Each wiring trace has a protruding portion which protrudes onto the first ceramic layer surrounded by the second ceramic layer when viewed from above. An insulating coat is provided to cover a portion of a concave corner formed by the second ceramic layer and the first ceramic layer.

    Chip and pinout design method therefor
    7.
    发明授权
    Chip and pinout design method therefor 有权

    公开(公告)号：US11928414B2

    公开(公告)日：2024-03-12

    申请号：US18270215

    申请日：2021-11-30

    Applicant: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.

    Inventor： Lei Liang ,  Qingsong Qin

    IPC: G06F30/30 ,  G06F30/392 ,  G06F30/394 ,  H05K3/00 ,  G06F113/18 ,  G06F115/12

    CPC classification number: G06F30/394 ,  G06F30/392 ,  H05K3/0005 ,  G06F2113/18 ,  G06F2115/12 ,  H05K2201/09227

    Abstract: Provided are a chip and a pin line-out design method therefor, which are applied to a BGA packaged chip. The method includes: according to pin position information and pin definition information of a chip, determining a number of circuit board layers required for pin line-out of the chip (S1); allocating line-out layers to pins of the chip in their respective circuit boards (S2); and according to a pin density and transmission line width requirement of the chip, determining a specification of a via hole in each circuit board for leading the pin of the chip out to the corresponding line-out layer, to perform a corresponding line-out design on the basis of the via hole (S3). It may be seen that the described unified pin line-out design for the BGA packaged chip is more refined, and the quality of the line-out design of the pins of the chip is ensured.

    DISPLAY PANEL AND DISPLAY APPARATUS
    8.
    发明公开
    DISPLAY PANEL AND DISPLAY APPARATUS 审中-公开

    公开(公告)号：US20240080973A1

    公开(公告)日：2024-03-07

    申请号：US18075700

    申请日：2022-12-06

    Applicant: Wuhan Tianma Micro-Electronics Co., Ltd.

    Inventor： Yangzhao MA ,  Hao DAI

    IPC: H05K1/02

    CPC classification number: H05K1/0296 ,  H05K2201/09227

    Abstract: A display panel and a display apparatus are provided in the present disclosure. The display panel includes a display region, a functional device configuration region, and a plurality of data lines which extends along a first direction. A second data line of the plurality of data lines includes a first sub-data-line and a second sub-data-line; and along the first direction, the first sub-data-line and the second sub-data-line in a same second data line are respectively arranged on two sides of the functional device configuration region. The display panel further includes first-wirings extending along the first direction and second-wirings extending along a second direction. One end of the second-wiring is electrically connected to the first-wiring, and another end of the second-wiring is electrically connected to a first data line of the first data lines; and the second-wirings include first sub-second-wirings and second sub-second-wirings.

    WIRING BASE AND ELECTRONIC DEVICE
    9.
    发明公开
    WIRING BASE AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20240074035A1

    公开(公告)日：2024-02-29

    申请号：US18029023

    申请日：2021-09-28

    Applicant: KYOCERA Corporation

    Inventor： Yoshiki KAWAZU ,  Taito KIMURA

    IPC: H05K1/02 ,  H01P3/08

    CPC classification number: H05K1/0219 ,  H01P3/081 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/09672 ,  H05K2201/0969

    Abstract: A wiring base includes a base, a signal conductor, and a ground conductor including a first ground conductor. The base includes a first surface, a first region, and a second region. The first region is located near an outer side of the first surface. An external board is mounted in the first region. The second region is other than the first region. The signal conductor extends through a region including the first region of the first surface in a first direction away from the outer side. The first ground conductor is located in the base at a distance from the signal conductor of less than ¼ of a wavelength of a high-frequency signal. The high-frequency signal is transmitted through the signal conductor. The first ground conductor includes a first grid portion at a first location overlapping the first region and at least a portion of the signal conductor.

    ELECTRONIC DEVICE
    10.
    发明公开
    ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230378096A1

    公开(公告)日：2023-11-23

    申请号：US18299834

    申请日：2023-04-13

    Applicant: InnoLux Corporation

    Inventor： Yu-Chih CHEN ,  Nai-Hsuan CHENG ,  Shao-Hong CHEN

    IPC: H01L23/00 ,  H01L27/12 ,  H05K1/02

    CPC classification number: H01L23/562 ,  H01L27/124 ,  H05K1/0219 ,  H05K2201/0715 ,  H05K2201/09227

    Abstract: An electronic device is provided. The electronic device includes a substrate, a first conductive layer, an insulating layer, and a second conductive layer. The first conductive layer is disposed on the substrate. The first conductive layer has a first connection wire and a second connection wire. In a cycle, the first connection wire transmits a positive polarity signal and the second connection wire transmits a negative polarity signal. The insulating layer is disposed on the first conductive layer. The second conductive layer is disposed on the insulating layer. The second conductive layer includes a plurality of portions covering the first connection wire and the second connection wire. In addition, the number of first connection wire covered by each of the plurality of portions is equal to the number of second connection wire covered by each of the plurality of portions.

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