Multi-tiered metadata scheme for a data storage array
    1.
    发明授权
    Multi-tiered metadata scheme for a data storage array 有权
    用于数据存储阵列的多层次元数据方案

    公开(公告)号:US08402205B2

    公开(公告)日:2013-03-19

    申请号:US12726486

    申请日:2010-03-18

    IPC分类号: G06F12/00 G06F12/02 G06F12/10

    摘要: Method and apparatus for managing metadata associated with a data storage array. In accordance with various embodiments, a group of user data blocks are stored to memory cells at a selected physical address of the array. A multi-tiered metadata scheme is used to generate metadata which describes the selected physical address of the user data blocks. The multi-tiered metadata scheme provides an upper tier metadata format adapted for groups of N user data blocks, and a lower tier metadata format adapted for groups of M user data blocks where M is less than N. The generated metadata is formatted in accordance with a selected one of the upper or lower tier metadata formats in relation to a total number of the user data blocks in the group.

    摘要翻译: 用于管理与数据存储阵列相关联的元数据的方法和装置。 根据各种实施例,一组用户数据块被存储到阵列的所选物理地址处的存储器单元。 使用多层元数据方案来生成描述用户数据块的选定物理地址的元数据。 多层元数据方案提供适用于N个用户数据块组的上层元数据格式,以及适用于M小于N的M个用户数据块组的较低层元数据格式。所生成的元数据根据 相对于组中的用户数据块的总数,选择的上层或下层元数据格式之一。

    Multi-Tiered Metadata Scheme for a Data Storage Array
    2.
    发明申请
    Multi-Tiered Metadata Scheme for a Data Storage Array 有权
    数据存储阵列的多层次元数据方案

    公开(公告)号:US20110231596A1

    公开(公告)日:2011-09-22

    申请号:US12726486

    申请日:2010-03-18

    IPC分类号: G06F12/00 G06F12/02 G06F12/10

    摘要: Method and apparatus for managing metadata associated with a data storage array. In accordance with various embodiments, a group of user data blocks are stored to memory cells at a selected physical address of the array. A multi-tiered metadata scheme is used to generate metadata which describes the selected physical address of the user data blocks. The multi-tiered metadata scheme provides an upper tier metadata format adapted for groups of N user data blocks, and a lower tier metadata format adapted for groups of M user data blocks where M is less than N. The generated metadata is formatted in accordance with a selected one of the upper or lower tier metadata formats in relation to a total number of the user data blocks in the group.

    摘要翻译: 用于管理与数据存储阵列相关联的元数据的方法和装置。 根据各种实施例,一组用户数据块被存储到阵列的所选物理地址处的存储器单元。 使用多层元数据方案来生成描述用户数据块的选定物理地址的元数据。 多层元数据方案提供适用于N个用户数据块组的上层元数据格式,以及适用于M小于N的M个用户数据块组的较低层元数据格式。所生成的元数据根据 相对于组中的用户数据块的总数,选择的上层或下层元数据格式之一。

    FAULT TOLERANT STORAGE CONSERVING MEMORY WRITES TO HOST WRITES
    3.
    发明申请
    FAULT TOLERANT STORAGE CONSERVING MEMORY WRITES TO HOST WRITES 审中-公开
    容错存储保存存储器写入主机写入

    公开(公告)号:US20110258380A1

    公开(公告)日:2011-10-20

    申请号:US12763003

    申请日:2010-04-19

    IPC分类号: G06F12/16

    CPC分类号: G06F11/108

    摘要: A data storage apparatus and associated method involving a memory with a plurality of storage elements defining an associated set of stored data, and memory control logic that, responsive to a request to store first data in a first storage element of the plurality of storage elements, computes without storing to any of the plurality of storage elements first redundancy data for the associated set of stored data inclusive of the first data.

    摘要翻译: 一种数据存储装置和相关联的方法,涉及具有定义相关联的存储数据集合的多个存储元件的存储器以及响应于将第一数据存储在多个存储元件的第一存储元件中的请求的存储器控​​制逻辑, 计算不存储到多个存储元件中的任何一个的用于包括第一数据的相关联的存储数据集合的第一冗余数据。

    Write delay stabilization
    4.
    发明授权
    Write delay stabilization 有权
    写延迟稳定

    公开(公告)号:US08582226B2

    公开(公告)日:2013-11-12

    申请号:US13421547

    申请日:2012-03-15

    IPC分类号: G11B5/02

    CPC分类号: G11B5/746 G11B5/012

    摘要: Apparatus and method for write delay stabilization. A write driver is adapted to output bipolar write currents to write data to a memory. A preconditioning circuit is adapted to output first and second thermal preconditioning currents through the write driver to stabilize a write delay associated with the write driver to a steady-state level prior to the writing of data to the memory.

    摘要翻译: 写延迟稳定的装置和方法。 写驱动器适于输出双极写入电流以将数据写入存储器。 预处理电路适于通过写入驱动器输出第一和第二热预处理电流,以便在将数据写入存储器之前将与写入驱动器相关联的写入延迟稳定在稳定状态。

    WRITE SYNCHRONIZATION PHASE CALIBRATION FOR STORAGE MEDIA
    5.
    发明申请
    WRITE SYNCHRONIZATION PHASE CALIBRATION FOR STORAGE MEDIA 有权
    存储介质的写同步相位校准

    公开(公告)号:US20100202079A1

    公开(公告)日:2010-08-12

    申请号:US12475001

    申请日:2009-05-29

    IPC分类号: G11B5/09

    摘要: A technique is described for write synchronization phase calibration for storage media (e.g., bit patterned media). In one embodiment, a calibration write clock signal may be generated at a frequency offset from a nominal dot frequency of a bit patterned storage media. A periodic signal that was written to the media synchronous to the calibration write clock signal may then be read and mixed with a reference periodic signal at the nominal dot frequency to obtain a difference signal. This difference signal may be demodulated to determine a phase correction for write synchronization to the media.

    摘要翻译: 描述了用于存储介质(例如,位图形介质)的写入同步相位校准的技术。 在一个实施例中,校准写时钟信号可以以与位图形存储介质的标称点频率偏移的频率产生。 然后可以将与校准写入时钟信号同步的写入媒体的周期性信号读取并以标称点频率与参考周期信号混合,以获得差分信号。 该差分信号可以被解调以确定用于与介质的写入同步的相位校正。

    RANDOM NUMBER GENERATION USING SWITCHING REGULATORS
    6.
    发明申请
    RANDOM NUMBER GENERATION USING SWITCHING REGULATORS 失效
    使用切换调节器的随机数生成

    公开(公告)号:US20130124591A1

    公开(公告)日:2013-05-16

    申请号:US13297009

    申请日:2011-11-15

    IPC分类号: G06F7/58

    CPC分类号: G06F7/588

    摘要: Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.

    摘要翻译: 使用与电路硬件相关的熵特性生成随机数。 与一种方法一致,使用开关电压调节器电路来产生随机数。 产生响应于开关稳压器电路的开关状态的数据。 然后从生成的数据生成多位随机数。

    Interspersed phase-locked loop fields for data storage media synchronization
    7.
    发明授权
    Interspersed phase-locked loop fields for data storage media synchronization 有权
    用于数据存储介质同步的散置锁相环域

    公开(公告)号:US07969676B2

    公开(公告)日:2011-06-28

    申请号:US12267305

    申请日:2008-11-07

    IPC分类号: G11B27/36

    摘要: Techniques are described for providing media-referenced timing for operations on a data storage medium. In particular, Phase-Locked Loop (PLL) synchronization fields may be interspersed within data fields of the medium and may be read to obtain timing measurements. The PLL fields are illustratively pre-recorded at predetermined intervals on the medium and have a fixed number of dots of the bit patterned medium between the PLL fields. Phase and frequency of a write clock may be controlled based on the read PLL fields to translate the timing measurements from the PLL fields into phase and frequency corrections to synchronize the write clock to the data storage medium.

    摘要翻译: 描述技术来提供用于数据存储介质上的操作的媒体参考定时。 特别地,锁相环(PLL)同步字段可以散布在介质的数据字段内,并且可以被读取以获得定时测量。 说明性地在介质上以预定的间隔预先记录PLL场,并且在PLL场之间具有固定数量的位图案化介质的点。 可以基于读取的PLL字段来控制写时钟的相位和频率,以将来自PLL场的定时测量值转换为相位和频率校正,以将写入时钟同步到数据存储介质。

    WRITE PRECOMPENSATION SYSTEM
    8.
    发明申请
    WRITE PRECOMPENSATION SYSTEM 审中-公开
    写预认证系统

    公开(公告)号:US20100118433A1

    公开(公告)日:2010-05-13

    申请号:US12266677

    申请日:2008-11-07

    IPC分类号: G11B21/02

    摘要: A write precompensation system comprises a write precompensation processor that calculates time shift information for the timing of individual write current transitions at a write head to coincide with a media pattern under the write head and a write precompensation controller that shifts the individual write current transitions in accordance with the time shift information.

    摘要翻译: 一种写入预补偿系统,包括一个写入预补偿处理器,用于计算在写入头处的各个写入电流转换的定时的时间偏移信息,以与写入头下面的介质模式一致;以及写入预补偿控制器, 与时间偏移信息。

    ELIMINATING SECTOR SYNCHRONIZATION FIELDS FOR BIT PATTERNED MEDIA
    9.
    发明申请
    ELIMINATING SECTOR SYNCHRONIZATION FIELDS FOR BIT PATTERNED MEDIA 审中-公开
    消除位图形媒体的行业同步字段

    公开(公告)号:US20100118427A1

    公开(公告)日:2010-05-13

    申请号:US12267215

    申请日:2008-11-07

    IPC分类号: G11B5/09

    摘要: Clock synchronization techniques are described for data storage media, particularly for the tolerances of efficient use of bit patterned media (BPM) capacity. In particular, techniques are described where position of a read-write head and timing of a write and/or read clock is determined within a fraction of a dot of the underlying media. The techniques obviate the requirement for the fields conventionally written preceding a data sector to provide bit synchronization and symbol framing (sector synchronization fields).

    摘要翻译: 为数据存储介质描述了时钟同步技术,特别是针对有效使用位图形介质(BPM)容量的公差。 特别地,描述了技术,其中读写头的位置和写入和/或读取时钟的定时在底层介质的点的一小部分内被确定。 该技术避免了对数据扇区之前传统写入的字段提供位同步和符号成帧(扇区同步字段)的要求。

    Random number generation using switching regulators
    10.
    发明授权
    Random number generation using switching regulators 失效
    使用开关调节器产生随机数

    公开(公告)号:US08788551B2

    公开(公告)日:2014-07-22

    申请号:US13297009

    申请日:2011-11-15

    IPC分类号: G06F1/02

    CPC分类号: G06F7/588

    摘要: Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.

    摘要翻译: 使用与电路硬件相关的熵特性生成随机数。 与一种方法一致,使用开关电压调节器电路来产生随机数。 产生响应于开关稳压器电路的开关状态的数据。 然后从生成的数据生成多位随机数。