公开(公告)号：US20210019082A1

公开(公告)日：2021-01-21

申请号：US16514195

申请日：2019-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： AMIT BERMAN ,  ARIEL DOUBCHAK ,  NOAM LIVNE

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C13/00

Abstract: A memory system including a nonvolatile memory (NVM) device and a controller is provided. The NVM device includes a main region and a spare region. The controller writes write data to a selected row of the main region, determines whether the written row is bad, and writes the write data to a spare address in the spare region and writes the spare address to the bad row, when the written row is determined to be bad.

公开(公告)号：US20240157933A1

公开(公告)日：2024-05-16

申请号：US18511690

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： AMIT BERMAN ,  SARIT BUZAGLO ,  ARIEL DOUBCHAK

IPC: B60W30/06 ,  B60W40/06 ,  G08G1/14

CPC classification number: B60W30/06 ,  B60W40/06 ,  G08G1/144 ,  G08G1/146 ,  G08G1/148 ,  B60W2555/20

Abstract: A method of simplified successive cancellation list (SSCL) error decoding of S-polar codes includes representing an S-polar code as a perfect binary tree; providing a node v a vector αv(l) of soft information from a parent node; computing a vector αvl(l) of soft information for a left child of node v; providing node v with a vector βvl(l) of hard decisions from the left child and using it with αv(l) to create a soft information vector αv(l) and passing it to a right child of node v; providing node v with a vector βvr(l) of hard decisions from its right child and using it with βvl(l) to create a hard decision vector, βv of hard decisions, and passing it to its parent node; updating, when v is a ith leaf of the perfect tree, two path metrics, and selecting paths obtained by expanding current paths with a lowest path metric.

公开(公告)号：US20210344356A1

公开(公告)日：2021-11-04

申请号：US16865891

申请日：2020-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： AMIT BERMAN ,  ARIEL DOUBCHAK ,  ELI HAIM ,  EVGENY BLAICHMAN

IPC: H03M13/15 ,  H03M13/39 ,  H03M13/11 ,  G11C11/408 ,  G11C11/4074 ,  G11C7/02 ,  G06N3/08

Abstract: A mobile electronic device may include a memory device and a memory controller including an error correction code (ECC) encoder to encode data, a constrained channel encoder configured to encode an output of the ECC encoder based on one or more constraints, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data to the memory device, an expectation maximization (EM) signal processing component configured to receive a noisy multi-wordline voltage vector from the memory device and classify each bit of the vector with a log likelihood ration (LLR) value, a constrained channel decoder configured to receive a constrained vector from the EM signal processing component and produce an unconstrained vector, and an ECC decoder configured to decode the unconstrained vector. A machine learning interference cancellation component may operate based on or independent of input from the EM signal processing component.

公开(公告)号：US20200228144A1

公开(公告)日：2020-07-16

申请号：US16244944

申请日：2019-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： ARIEL DOUBCHAK ,  Dikla Shapiro ,  Amit Berman

IPC: H03M13/15 ,  H03M13/29 ,  H03M13/09 ,  G06F11/10 ,  G06F3/06

Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.