公开(公告)号：US20210019082A1

公开(公告)日：2021-01-21

申请号：US16514195

申请日：2019-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： AMIT BERMAN ,  ARIEL DOUBCHAK ,  NOAM LIVNE

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C13/00

Abstract: A memory system including a nonvolatile memory (NVM) device and a controller is provided. The NVM device includes a main region and a spare region. The controller writes write data to a selected row of the main region, determines whether the written row is bad, and writes the write data to a spare address in the spare region and writes the spare address to the bad row, when the written row is determined to be bad.

公开(公告)号：US20180102168A1

公开(公告)日：2018-04-12

申请号：US15288443

申请日：2016-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： IDDO NAISS ,  NOAM LIVNE ,  ELONA EREZ ,  JUN JIN KONG

IPC: G11C11/56 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C11/5642 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C29/52

Abstract: A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.