公开(公告)号：US20140135968A1

公开(公告)日：2014-05-15

申请号：US14018980

申请日：2013-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Ki LEE ,  Heeseok KIM ,  Sungho HAN

IPC: G05B13/00

CPC classification number: G05B19/4184 ,  G05B2219/31483 ,  G05B2219/32201 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/22 ,  Y02P90/26 ,  Y02P90/86

Abstract: In one example embodiment, a method of maintaining a semiconductor manufacturing line includes setting up a recipe for controlling an implementation of a unit process based on which at least one semiconductor device is manufactured by a manufacturing facility. The method further includes collecting reference data of the manufacturing facility being controlled according to the reference recipe and obtaining a statistical model of the reference data and a health index of the statistical model, the health index being a limit beyond which an output of the semiconductor manufacturing line decreases. The method further includes controlling the implementation of the unit process and obtaining monitoring data during the implementation of the unit process using the statistical mode. The method further includes renewing the statistical model based on the monitoring data.

Abstract translation: 在一个示例实施例中，维持半导体生产线的方法包括设置用于控制由制造设备制造至少一个半导体器件的单元工艺的实现的配方。 该方法还包括收集根据参考食谱进行控制的制造设施的参考数据，并且获得参考数据的统计模型和统计模型的健康指数，健康指数是超出该限制的半导体制造的输出 线减少。 该方法还包括在使用统计模式执行单元处理期间控制单元处理的实现并获得监视数据。 该方法还包括基于监视数据更新统计模型。

公开(公告)号：US20140001625A1

公开(公告)日：2014-01-02

申请号：US13933398

申请日：2013-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAUK HAN ,  Ho-Ki LEE ,  HyunSeok LIM ,  Kihyun YUN ,  MYOUNGBUM LEE ,  Jeonggil LEE ,  Tai-Soo LIM

IPC: H01L23/49

CPC classification number: H01L23/49 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: A semiconductor device may include a contact mold layer on a substrate, the contact mold layer defining first and second contact portions on the substrate, a wire mold layer on the contact mold layer, and first and second wires penetrating the wire mold layer and extending in a first direction, the first and second wires contacting the respective first and second contact portions and the contact mold layer. The first and second wires may be arranged in an alternating manner, and the first and second contact portions may be arranged to have a zigzag configuration. Each of the first and second contact portions may include a conductive pattern and a barrier pattern, and the barrier pattern may have a top surface lower than a top surface of the contact mold layer.

Abstract translation: 半导体器件可以包括在基板上的接触模制层，接触模具层限定基板上的第一和第二接触部分，接触模具层上的线模层，以及穿过线模层的第一和第二导线 第一方向，第一和第二线接触相应的第一和第二接触部分和接触模具层。 第一和第二导线可以以交替的方式布置，并且第一和第二接触部分可以被布置成具有锯齿形构造。 第一和第二接触部分中的每一个可以包括导电图案和阻挡图案，并且阻挡图案可以具有比接触模制层的顶表面低的顶表面。