公开(公告)号：US10541302B2

公开(公告)日：2020-01-21

申请号：US15881863

申请日：2018-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic Yoon ,  Ho-in Lee ,  Ki-seok Lee ,  Je-min Park

IPC: H01L21/762 ,  H01L29/06 ,  H01L27/108 ,  G11C11/408

Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

公开(公告)号：US20180350905A1

公开(公告)日：2018-12-06

申请号：US15881863

申请日：2018-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic Yoon ,  Ho-in Lee ,  Ki-seok Lee ,  Je-min Park

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

CPC classification number: H01L29/0649 ,  G11C11/4085 ,  H01L21/76232 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897

Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

公开(公告)号：US20180175143A1

公开(公告)日：2018-06-21

申请号：US15833031

申请日：2017-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-sic YOON ,  Ki-seok Lee ,  Ki-wook Jung ,  Dong-oh Kim ,  Ho-in Lee ,  Je-min Park ,  Seok-han Park ,  Augustin Hong ,  Ju-yeon Jang ,  Hyeon-ok Jung ,  Yu-jin Seo

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/0206 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/4236

Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.

公开(公告)号：US11264454B2

公开(公告)日：2022-03-01

申请号：US16719175

申请日：2019-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic Yoon ,  Ho-in Lee ,  Ki-seok Lee ,  Je-min Park

IPC: H01L27/11573 ,  H01L29/06 ,  H01L21/762 ,  H01L27/108 ,  G11C11/408

Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.