公开(公告)号：US10896967B2

公开(公告)日：2021-01-19

申请号：US16404996

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic Yoon ,  Dong-oh Kim ,  Je-min Park ,  Ki-seok Lee

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/51

Abstract: An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.

公开(公告)号：US10784266B2

公开(公告)日：2020-09-22

申请号：US16181510

申请日：2018-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-oh Kim ,  Ki-seok Lee ,  Chan-sic Yoon ,  Je-min Park ,  Woo-song Ahn

IPC: H01L27/108 ,  H01L23/538 ,  H01L29/49 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L29/66

Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.

公开(公告)号：US20190355728A1

公开(公告)日：2019-11-21

申请号：US16181510

申请日：2018-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-oh Kim ,  Ki-seok Lee ,  Chan-sic Yoon ,  Je-min Park ,  Woo-song Ahn

IPC: H01L27/108 ,  H01L23/538 ,  H01L29/49

Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.

公开(公告)号：US20180175143A1

公开(公告)日：2018-06-21

申请号：US15833031

申请日：2017-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-sic YOON ,  Ki-seok Lee ,  Ki-wook Jung ,  Dong-oh Kim ,  Ho-in Lee ,  Je-min Park ,  Seok-han Park ,  Augustin Hong ,  Ju-yeon Jang ,  Hyeon-ok Jung ,  Yu-jin Seo

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/0206 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/4236

Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.