公开(公告)号：US09659790B2

公开(公告)日：2017-05-23

申请号：US15152096

申请日：2016-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-han Park

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/02 ,  H01L27/108

CPC classification number: H01L21/31144 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31133 ,  H01L21/32139 ,  H01L27/10852 ,  H01L27/10894

Abstract: A method of forming a pattern, the method including forming a mask layer on a feature layer on a substrate; forming guides regularly arranged with a first pitch on the mask layer in a first region and dummy guides regularly arranged with the first pitch on the mask layer in a second region spaced apart from the first region with a separation region therebetween, the separation region having a width greater than the first pitch; forming a block copolymer layer on the mask layer; phase-separating the block copolymer layer to form a self-assembled layer; forming a mask pattern by etching the mask layer using the self-assembled layer; and patterning the feature layer by transferring a shape of the mask pattern to the feature layer in the first region while blocking the shape of the mask pattern from being transferred to the feature layer in the second region.

公开(公告)号：US10727233B2

公开(公告)日：2020-07-28

申请号：US16043398

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-han Park

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/764 ,  H01L21/768 ,  H01L21/311 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02

Abstract: An integrated circuit device includes: a conductive line structure including a conductive line and an insulating capping pattern; and an insulating spacer including an inner spacer and a first insulating spacer, the inner spacer and the first insulating spacer on a sidewall of the conductive line structure. The first insulating spacer includes: a slit portion; a lower insulating portion spaced apart from the inner spacer such that a separation distance between a portion of the lower insulating portion and the inner spacer decreases with increasing vertical distance from the substrate; and an upper insulating portion contacting the inner spacer. A method of forming the insulating spacer includes: forming a polymer layer on the inner spacer; forming a first insulating spacer layer which contacts each of the inner spacer and the polymer layer; and forming a first insulating spacer by partially removing the first insulating spacer layer.

公开(公告)号：US10546810B2

公开(公告)日：2020-01-28

申请号：US16005850

申请日：2018-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-han Park

IPC: H01L23/522 ,  H01L21/311 ,  H01L21/308 ,  H01L21/027

Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.

公开(公告)号：US09768032B2

公开(公告)日：2017-09-19

申请号：US15083321

申请日：2016-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-han Park

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/02 ,  H01L27/108

CPC classification number: H01L21/31144 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31133 ,  H01L21/32139 ,  H01L27/10847 ,  H01L27/10897

Abstract: A method of forming a pattern including forming a feature layer on a substrate having first and second regions; forming a first guide pattern on the first region, the first guide pattern having openings therein, the openings exposing the feature layer; forming a second guide pattern covering the feature layer exposed through the first guide pattern on the first region and covering the second region; forming a block copolymer layer covering the first guide pattern and the second guide pattern on the first and second regions; phase-separating the block copolymer layer to form first vertical domains and a second vertical domain; removing the first vertical domains on the first region; and etching the first guide pattern and the feature layer using the second vertical domain as an etch mask on the first region to form a feature pattern having holes therein.

公开(公告)号：US10937729B2

公开(公告)日：2021-03-02

申请号：US16714953

申请日：2019-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-han Park

IPC: H01L23/522 ,  H01L21/311 ,  H01L21/308 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105

Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.

公开(公告)号：US20190122980A1

公开(公告)日：2019-04-25

申请号：US16005850

申请日：2018-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-han Park

IPC: H01L23/522 ,  H01L21/027 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L23/5222 ,  H01L21/02118 ,  H01L21/0273 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31144

Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.

公开(公告)号：US20180175143A1

公开(公告)日：2018-06-21

申请号：US15833031

申请日：2017-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-sic YOON ,  Ki-seok Lee ,  Ki-wook Jung ,  Dong-oh Kim ,  Ho-in Lee ,  Je-min Park ,  Seok-han Park ,  Augustin Hong ,  Ju-yeon Jang ,  Hyeon-ok Jung ,  Yu-jin Seo

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/0206 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/4236

Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.

公开(公告)号：US11018020B2

公开(公告)日：2021-05-25

申请号：US16385386

申请日：2019-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-han Park

IPC: H01L21/311 ,  H01L21/768 ,  H01L27/108 ,  H01L21/3105 ,  H01L21/56 ,  H01L49/02

Abstract: A method of fabricating an integrated circuit device includes forming a mold layer on a main surface of a substrate. A first hole is formed in the mold layer having a first inner wall that has a first tilt angle. A first conductive pattern is formed in the first hole. A block copolymer layer is formed on the mold layer and the first conductive pattern. A self-assembly layer is formed having a first domain and a second domain by phase separation of the block copolymer layer. The first domain covers the first conductive pattern and the second domain covers the mold layer. A second hole is formed by removing the first domain, the second hole having a second inner wall that has a second tilt angle. A second conductive pattern is formed in the second hole.

公开(公告)号：US20190123051A1

公开(公告)日：2019-04-25

申请号：US16043398

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-han Park

IPC: H01L27/108 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

Abstract: An integrated circuit device includes: a conductive line structure including a conductive line and an insulating capping pattern; and an insulating spacer including an inner spacer and a first insulating spacer, the inner spacer and the first insulating spacer on a sidewall of the conductive line structure. The first insulating spacer includes: a slit portion; a lower insulating portion spaced apart from the inner spacer such that a separation distance between a portion of the lower insulating portion and the inner spacer decreases with increasing vertical distance from the substrate; and an upper insulating portion contacting the inner spacer. A method of forming the insulating spacer includes: forming a polymer layer on the inner spacer; forming a first insulating spacer layer which contacts each of the inner spacer and the polymer layer; and forming a first insulating spacer by partially removing the first insulating spacer layer.

公开(公告)号：US09934986B2

公开(公告)日：2018-04-03

申请号：US15049268

申请日：2016-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-seop Shim ,  Seok-han Park ,  Bum-seok Seo

IPC: H01L21/331 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/033

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/32139

Abstract: Provided is a method of forming fine patterns, which is capable of easily forming a plurality of patterns repeatedly with a fine pitch when forming patterns necessary for manufacturing a highly integrated semiconductor device exceeding a resolution limit of a photolithography process.