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    Integrated circuit device including gate spacer structure
    1.
    发明授权
    Integrated circuit device including gate spacer structure 有权

    公开(公告)号：US10896967B2

    公开(公告)日：2021-01-19

    申请号：US16404996

    申请日：2019-05-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chan-sic Yoon ,  Dong-oh Kim ,  Je-min Park ,  Ki-seok Lee

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/51

    Abstract: An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.

    Semiconductor device including landing pad
    3.
    发明授权
    Semiconductor device including landing pad 有权
    半导体装置包括着陆垫

    公开(公告)号：US09362289B2

    公开(公告)日：2016-06-07

    申请号：US14581012

    申请日：2014-12-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Je-min Park

    IPC: H01L27/108

    CPC classification number: H01L27/10876 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The semiconductor device includes a plurality of conductive line structures including a plurality of conductive lines spaced apart from a substrate with an insulating film there between and insulating capping layers that are formed on each of plurality of conductive lines; an insulating spacer that is disposed between the plurality of conductive line structures and covers both side walls of each of the plurality of conductive line structures to define a contact hole having a first width in a first direction parallel to an upper surface of the substrate; a contact plug filling a portion of the contact hole; and a landing pad that is connected to the contact plug and vertically overlapping with one of the plurality of conductive line structures.

    Abstract translation: 半导体器件包括多个导线结构，其包括与衬底隔开的多个导线，其间具有绝缘膜，绝缘覆盖层形成在多条导线中的每一条上; 绝缘间隔件，其设置在所述多个导电线结构之间并且覆盖所述多个导电线结构中的每一个的两个侧壁，以限定在平行于所述基板的上表面的第一方向上具有第一宽度的接触孔; 接触塞，其填充接触孔的一部分; 以及连接到所述接触插塞并与所述多个导线结构中的一个垂直重叠的着陆焊盘。

    INTEGRATED CIRCUIT DEVICE
    4.
    发明申请
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20190355728A1

    公开(公告)日：2019-11-21

    申请号：US16181510

    申请日：2018-11-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-oh Kim ,  Ki-seok Lee ,  Chan-sic Yoon ,  Je-min Park ,  Woo-song Ahn

    IPC: H01L27/108 ,  H01L23/538 ,  H01L29/49

    Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20180350905A1

    公开(公告)日：2018-12-06

    申请号：US15881863

    申请日：2018-01-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chan-sic Yoon ,  Ho-in Lee ,  Ki-seok Lee ,  Je-min Park

    IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

    CPC classification number: H01L29/0649 ,  G11C11/4085 ,  H01L21/76232 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897

    Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

    Semiconductor devices including conductive plug
    7.
    发明授权
    Semiconductor devices including conductive plug 有权
    半导体器件包括导电插头

    公开(公告)号：US09548260B2

    公开(公告)日：2017-01-17

    申请号：US14175305

    申请日：2014-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Je-min Park ,  Dae-ik Kim ,  Ji-young Kim ,  Nak-jin Son ,  Yoo-sang Hwang

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/485 ,  H01L27/108 ,  H01L21/768 ,  H01L29/417

    CPC classification number: H01L23/485 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/41791 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug.

    Abstract translation: 半导体器件包括具有目标连接区域的衬底; 导电线，其具有通过至少绝缘层与衬底间隔开的第一侧壁和将导电线电连接到目标连接区域的导电插塞结构，其中导电插塞包括第一导电插塞，第一导电插塞具有第一侧壁 ，与基板的目标连接区域接触的底表面和面对导电线的第一侧壁的第二侧壁，以及在导线和第一导电塞之间的第二导电塞。 第二导电插头接触导电线的第一侧壁和第一导电插塞的第二侧壁。

    Semiconductor device including landing pad
    9.
    发明授权
    Semiconductor device including landing pad 有权
    半导体装置包括着陆垫

    公开(公告)号：US09437560B2

    公开(公告)日：2016-09-06

    申请号：US14606245

    申请日：2015-01-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Je-min Park ,  Yoo-sang Hwang

    IPC: H01L23/52 ,  H01L23/00 ,  H01L27/108

    CPC classification number: H01L23/528 ,  H01L24/02 ,  H01L24/08 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/15313

    Abstract: A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a contact hole. The insulating spacer structure is adjacent a side wall of at least one of the conductive lines. The device also includes an insulating pattern on the conductive lines and insulating spacer structure, and another insulating pattern defining a landing pad hole connected to the contact hole. A contact plug is formed in the contact hole and connects to the active area. A landing pad is formed in the landing pad hole and connects to the contact plug. The landing pad vertically overlaps one of the pair of conductive line structures.

    Abstract translation: 半导体器件包括与衬底间隔开的导线，以及在导线之间的绝缘间隔结构，并限定接触孔。 绝缘间隔物结构邻近至少一条导电线的侧壁。 该装置还包括导电线上的绝缘图案和绝缘间隔结构，以及限定连接到接触孔的着陆焊盘孔的另一绝缘图案。 接触插塞形成在接触孔中并且连接到有源区域。 着陆垫形成在着陆垫孔中并连接到接触塞。 着陆垫垂直地重叠一对导线结构之一。

    Integrated circuit device and method of manufacturing the same
    10.
    发明授权
    Integrated circuit device and method of manufacturing the same 有权

    公开(公告)号：US11264454B2

    公开(公告)日：2022-03-01

    申请号：US16719175

    申请日：2019-12-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chan-sic Yoon ,  Ho-in Lee ,  Ki-seok Lee ,  Je-min Park

    IPC: H01L27/11573 ,  H01L29/06 ,  H01L21/762 ,  H01L27/108 ,  G11C11/408

    Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

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