公开(公告)号：US20240349483A1

公开(公告)日：2024-10-17

申请号：US18415754

申请日：2024-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOHYUN PARK ,  Inwoo KIM ,  Sangho LEE ,  Jihun LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: A semiconductor device includes an active pattern on a substrate; a bit line structure on a central portion of the active pattern; a first spacer structure and a second spacer structure disposed on a first sidewall and a second sidewall, respectively, of the bit line structure, the first sidewall and the second sidewall of the bit line structure facing each other in the first direction; a lower contact plug on each of opposite end portions of the active pattern; and an upper contact plug on the lower contact plug. The upper contact plug may include a conductive pattern; and a conductive spacer covering a lower surface of the conductive pattern, wherein the conductive spacer contacts an outer sidewall of the first spacer structure, and does not contact an outer sidewall of the second spacer structure.

公开(公告)号：US20220344341A1

公开(公告)日：2022-10-27

申请号：US17558855

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huijung KIM ,  Myeongdong LEE ,  Inwoo KIM ,  Sunghee HAN

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device that includes a substrate including an active region and a contact recess. A gate electrode is disposed in the substrate and extends in a first direction. A bit line structure intersects the gate electrode and extends in a second direction intersecting the first direction. The bit line structure includes a direct contact disposed in the contact recess. A buried contact is disposed on the substrate and is electrically connected to the active region. A spacer structure is disposed between the bit line structure and the buried contact. The spacer structure includes a buried spacer disposed on a lateral side surface of the direct contact, and an air gap disposed on the buried spacer. The air gap exposes a lateral side surface of the bit line structure.

公开(公告)号：US20250040129A1

公开(公告)日：2025-01-30

申请号：US18655731

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungbo KO ,  Inwoo KIM ,  Jongmin KIM ,  Kiseok LEE ,  Minyoung LEE ,  Seongtak CHO ,  Inho CHA

IPC: H10B12/00

Abstract: A semiconductor device may include a device isolation layer on a side of the active region, a gate trench intersecting the active region, a gate structure in the gate trench, a bit line electrically connected to a first region of the active region, and a pad pattern electrically connected to a second region of the active region. An upper surface of the second region may be higher than an upper surface of the first region and lower than an upper surface of the bit line. A width of the bit line may be greater in an upper region than a lower region thereof. The pad pattern may contact upper and side surfaces of the second region. An upper surface of the pad pattern may be higher than an upper surface of the bit line. The gate trench may be between the first and second regions of the active region.