公开(公告)号：US20210296237A1

公开(公告)日：2021-09-23

申请号：US17097337

申请日：2020-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYO-SUB KIM ,  SOHYUN PARK ,  DAEWON KIM ,  DONGOH KIM ,  EUN A KIM ,  CHULKWON PARK ,  TAEJIN PARK ,  KISEOK LEE ,  SUNGHEE HAN

IPC: H01L23/535 ,  H01L27/108 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

公开(公告)号：US20230153252A1

公开(公告)日：2023-05-18

申请号：US17895303

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOHYUN PARK ,  YUNHO YOUM ,  MYUNGSIK CHOI

IPC: G06F12/14 ,  G11C17/16 ,  G11C17/18

CPC classification number: G06F12/1466 ,  G11C17/16 ,  G11C17/18 ,  H03K19/20

Abstract: A semiconductor device includes a one-time programmable (OTP) memory device, a key register and a key protection control logic. The OTP memory device stores a secret value, a key protection bit indicating whether to protect the secret value, and an end of life bit indicating whether to discard the semiconductor device. The key register loads the secret value from the OTP memory device and stores the secret value. The key protection control logic controls loading of the secret value from the OTP memory device to the key register based on the key protection bit and the end of life bit. Security of the secret value is enhanced and utilization of the secret value is optimized using the key protection bit and the end of life bit.

公开(公告)号：US20210296321A1

公开(公告)日：2021-09-23

申请号：US17202465

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： INKYOUNG HEO ,  HYO-SUB KIM ,  SOHYUN PARK ,  TAEJIN PARK ,  SEUNG-HEON LEE ,  YOUN-SEOK CHOI ,  SUNGHEE HAN ,  YOOSANG HWANG

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

公开(公告)号：US20240349483A1

公开(公告)日：2024-10-17

申请号：US18415754

申请日：2024-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOHYUN PARK ,  Inwoo KIM ,  Sangho LEE ,  Jihun LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: A semiconductor device includes an active pattern on a substrate; a bit line structure on a central portion of the active pattern; a first spacer structure and a second spacer structure disposed on a first sidewall and a second sidewall, respectively, of the bit line structure, the first sidewall and the second sidewall of the bit line structure facing each other in the first direction; a lower contact plug on each of opposite end portions of the active pattern; and an upper contact plug on the lower contact plug. The upper contact plug may include a conductive pattern; and a conductive spacer covering a lower surface of the conductive pattern, wherein the conductive spacer contacts an outer sidewall of the first spacer structure, and does not contact an outer sidewall of the second spacer structure.

公开(公告)号：US20230253315A1

公开(公告)日：2023-08-10

申请号：US18133575

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEJIN PARK ,  KEUNNAM KIM ,  SOHYUN PARK ,  JIN-HWAN CHUN ,  WOOYOUNG CHOI ,  SUNGHEE HAN ,  INKYOUNG HEO ,  YOOSANG HWANG

IPC: H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/528 ,  H01L29/0649 ,  G11C5/10 ,  H01L29/4236 ,  H01L21/76831 ,  H10B12/485

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20210273048A1

公开(公告)日：2021-09-02

申请号：US16996282

申请日：2020-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEJIN PARK ,  CHULKWON PARK ,  SOYEONG KIM ,  EUN A KIM ,  HYO-SUB KIM ,  SOHYUN PARK ,  SUNGHEE HAN ,  YOOSANG HWANG

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/28 ,  H01L29/41

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.