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公开(公告)号：US20200285887A1
公开(公告)日：2020-09-10
申请号：US16884232
申请日：2020-05-27
Inventor： Sehwan LEE , Leesup KIM , Hyeonuk KIM , Jaehyeong SIM , Yeongjae CHOI
Abstract: A processor-implemented neural network method includes: obtaining, from a memory, data of an input feature map and kernels having a binary-weight, wherein the kernels are to be processed in a layer of a neural network; decomposing each of the kernels into a first type sub-kernel reconstructed with weights of a same sign, and a second type sub-kernel for correcting a difference between a respective kernel, among the kernels, and the first type sub-kernel; performing a convolution operation by using the input feature map and the first type sub-kernels and the second type sub-kernels decomposed from each of the kernels; and obtaining an output feature map by combining results of the convolution operation.
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Patent Agency Ranking
公开(公告)号：US20220083390A1
公开(公告)日：2022-03-17
申请号：US17223139
申请日：2021-04-06
Applicant: SAMSUNG ELECTRONICS CO., LTD
Inventor： Jae-Eon JO , Hyung-Dal KWON , Hanmin PARK , Jaehyeong SIM , Seung Wook LEE
IPC: G06F9/50 , G06N3/04 , G06N3/063 , G06F9/48 , G06F1/3237
Abstract: A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.
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公开(公告)号：US20190065896A1
公开(公告)日：2019-02-28
申请号：US16110664
申请日：2018-08-23
Inventor： Sehwan LEE , Leesup KIM , Hyeonuk KIM , Jaehyeong SIM , Yeongjae CHOI
CPC classification number: G06K9/623 , G06K9/6251 , G06K9/6267 , G06N3/04 , G06N3/0454 , G06N3/063
Abstract: A processor-implemented neural network method includes: obtaining, from a memory, data an input feature map and kernels having a binary-weight, wherein the kernels are to be processed in a layer of a neural network; decomposing each of the kernels into a first type sub-kernel reconstructed with weights of a same sign, and a second type sub-kernel for correcting a difference between a respective kernel, among the kernels, and the first type sub-kernel; performing a convolution operation by using the input feature map and the first type sub-kernels and the second type sub-kernels decomposed from each of the kernels; and obtaining an output feature map by combining results of the convolution operation.
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公开(公告)号：US20220164164A1
公开(公告)日：2022-05-26
申请号：US17356771
申请日：2021-06-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyung-Dal KWON , Ho Young KIM , Hanmin PARK , Jaehyeong SIM , Seung Wook LEE , Jae-Eon JO
Abstract: An apparatus with deep learning includes: a systolic adder tree including adder trees connected in row and column directions; and an input multiplexer connected to an input register of at least one of the adder trees and configured to determine column directional data movement between the adder trees based on operation modes.
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5.发明公开公开(公告)号：US20240004809A1
公开(公告)日：2024-01-04
申请号：US18364872
申请日：2023-08-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hanmin PARK , Hyung-Dal KWON , Jaehyeong SIM , Seungwook LEE , Jae-Eon JO
CPC classification number: G06F13/1668 , G06N3/04
Abstract: An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.
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6.发明申请公开(公告)号：US20220066960A1
公开(公告)日：2022-03-03
申请号：US17182439
申请日：2021-02-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hanmin PARK , Hyung-Dal KWON , Jaehyeong SIM , Seungwook LEE , Jae-Eon JO
Abstract: An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.
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