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公开(公告)号：US20150339059A1
公开(公告)日：2015-11-26
申请号：US14436344
申请日：2014-10-20
发明人： Byoungik KANG , Jinyoung PARK , Heesub SHIN , Seungwook LEE
IPC分类号： G06F3/06
CPC分类号： G06F3/0608 , G06F3/061 , G06F3/064 , G06F3/0659 , G06F3/0673 , G06F12/023 , G06F2212/401
摘要： Disclosed are a memory compression method of an electronic device and an apparatus thereof. The method for compressing memory in an electronic device may include: detecting a request for executing the first application; determining whether or not the memory compression is required for the execution of the first application; when the memory compression is required, compressing the memory corresponding to an application in progress in the background of the electronic device; and executing the first application.
摘要翻译： 公开了一种电子设备的记忆压缩方法及其装置。 用于压缩电子设备中的存储器的方法可以包括：检测执行第一应用的请求; 确定所述存储器压缩是否需要用于执行所述第一应用; 当需要存储器压缩时，在电子设备的背景中对与应用程序相对应的存储器进行压缩; 并执行第一应用。
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公开(公告)号：US20220035629A1
公开(公告)日：2022-02-03
申请号：US17102884
申请日：2020-11-24
发明人： Hyung-Dal KWON , Hanmin PARK , Seungwook LEE , Jae-Eon JO
摘要： Disclosed is an apparatus and method for performing deep learning operations. The apparatus includes a systolic array comprising multiplier accumulator (MAC) units, and a control circuit configured to control an operation of a multiplexer connected to at least one of the MAC units and operations of the MAC units according to a plurality of operation modes.
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公开(公告)号：US20170040365A1
公开(公告)日：2017-02-09
申请号：US15298204
申请日：2016-10-19
发明人： Seungwook LEE , Jungchak AHN , Youngwoo JUNG
IPC分类号： H01L27/146 , H01L29/423
CPC分类号： H01L27/14614 , H01L27/14603 , H01L27/14612 , H01L27/1463 , H01L27/14636 , H01L27/1464 , H01L27/14641 , H01L27/14645 , H01L27/14689 , H01L29/4236
摘要： A complementary metal-oxide-semiconductor (CMOS) image sensor is provided. The CMOS image sensor may include an epitaxial layer having a first conductivity type and having first and second surfaces, a first device isolation layer extending from the first surface to the second surface to define first and second pixel regions, a well impurity layer of a second conductivity type formed adjacent to the first surface and formed in the epitaxial layer of each of the first and second pixel regions, and a second device isolation layer formed in the well impurity layer in each of the first and second pixel regions to define first and second active portions spaced apart from each other in each of the first and second pixel regions.
摘要翻译： 提供了互补的金属氧化物半导体（CMOS）图像传感器。 CMOS图像传感器可以包括具有第一导电类型并具有第一和第二表面的外延层，从第一表面延伸到第二表面以限定第一和第二像素区域的第一器件隔离层，第二和第二表面的阱杂质层 导电类型，形成在第一表面附近并形成在第一和第二像素区域中的每一个的外延层中，以及第二器件隔离层，形成在第一和第二像素区域中的每一个中的阱杂质层中，以限定第一和第二像素区域 在第一和第二像素区域中的每一个中彼此间隔开的有源部分。
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4.发明公开公开(公告)号：US20240004809A1
公开(公告)日：2024-01-04
申请号：US18364872
申请日：2023-08-03
发明人： Hanmin PARK , Hyung-Dal KWON , Jaehyeong SIM , Seungwook LEE , Jae-Eon JO
CPC分类号： G06F13/1668 , G06N3/04
摘要： An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.
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5.发明申请公开(公告)号：US20220066960A1
公开(公告)日：2022-03-03
申请号：US17182439
申请日：2021-02-23
发明人： Hanmin PARK , Hyung-Dal KWON , Jaehyeong SIM , Seungwook LEE , Jae-Eon JO
摘要： An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.
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6.发明申请METHOD AND DEVICE FOR MONITORING DATA INTEGRITY IN SHARED MEMORY ENVIRONMENT 审中-公开用于监测共享存储器环境中的数据完整性的方法和设备公开(公告)号：US20160196083A1
公开(公告)日：2016-07-07
申请号：US14911932
申请日：2014-08-14
发明人： Hansu CHO , Brent ByungHoon KANG , Yunheung PAEK , Seungwook LEE , Junbum SHIN
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0619 , G06F3/0637 , G06F3/0659 , G06F3/0673 , G06F13/16 , G06F21/79 , H04L63/145
摘要： Provided is a method of memory access for a memory controller in an integrity monitoring system sharing memory with a host system. The memory access method may include: receiving a memory access command from a local processor of the integrity monitoring system; accessing a system memory of the host system according to the memory access command; receiving data corresponding to the memory access command from the host system; and forwarding the received data to the local processor, wherein the system memory includes a secure area, access to which is allowed when the memory controller receives a memory access command from the local processor. In a feature of the present invention, there are provided a method and apparatus that can monitor integrity of data processed in the host system in a SoC environment.
摘要翻译： 提供了一种用于与主机系统共享存储器的完整性监视系统中的存储器控制器的存储器访问的方法。 存储器访问方法可以包括：从完整性监视系统的本地处理器接收存储器访问命令; 根据存储器访问命令访问主机系统的系统存储器; 从所述主机系统接收对应于所述存储器访问命令的数据; 以及将所接收的数据转发到本地处理器，其中所述系统存储器包括安全区域，当所述存储器控制器从所述本地处理器接收到存储器访问命令时，所述访问被允许。 在本发明的特征中，提供了一种可以监视在SoC环境中在主机系统中处理的数据的完整性的方法和装置。
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公开(公告)号：US20230290838A1
公开(公告)日：2023-09-14
申请号：US18181071
申请日：2023-03-09
发明人： Taehun MYUNG , Yuri MASUOKA , Kihwang SON , Jaehun JEONG , Seulki PARK , Joongwon JEON , Kyunghoon JUNG , Yonghyun KO , Seungwook LEE
IPC分类号： H01L29/40 , H01L29/417 , H01L29/78
CPC分类号： H01L29/405 , H01L29/41791 , H01L29/7851
摘要： A semiconductor device includes a substrate including an active region, a first gate line and a second gate line in the active region, a first source/drain contact pattern in the active region at one side of the first gate line, a second source/drain contact pattern in the active region at one side of the second gate line, and a dummy source/drain contact pattern in the active region between the first gate line and the second gate line. The first gate line and the second gate line may be spaced apart from each other in the first direction and may extend in the second direction. The second direction may cross the first direction. A size of the dummy source/drain contact pattern may be less than a size of the first source/drain contact pattern and a size of the second source/drain contact pattern.
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公开(公告)号：US20220336506A1
公开(公告)日：2022-10-20
申请号：US17667620
申请日：2022-02-09
发明人： Seungwook LEE
IPC分类号： H01L27/146
摘要： Image sensors may include a base substrate including a substrate layer, a buried insulation layer on the substrate layer, and a semiconductor layer on the buried insulation layer, a photo sensing device in the substrate layer, a buried impurity region spaced apart from the photo sensing device in an upper portion of the substrate layer, a transfer gate including a vertical gate extending through the semiconductor layer and the buried insulation layer and extending into an inner portion of the substrate layer, which is between the photo sensing device and the buried impurity region, a planar gate on the semiconductor layer, and a gate insulation layer between the substrate layer and the planar gate.
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公开(公告)号：US20210250028A1
公开(公告)日：2021-08-12
申请号：US17242737
申请日：2021-04-28
发明人： Hyungdal KWON , Seungwook LEE , Youngnam HWANG
IPC分类号： H03K19/1776 , G06F30/327
摘要： An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.
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公开(公告)号：US20180300063A1
公开(公告)日：2018-10-18
申请号：US16018790
申请日：2018-06-26
发明人： Byoungik KANG , Jinyoung PARK , Heesub SHIN , Seungwook LEE
摘要： Disclosed are a memory compression method of an electronic device and an apparatus thereof. The method for compressing memory in an electronic device may include: detecting a request for executing the first application; determining whether or not the memory compression is required for the execution of the first application; when the memory compression is required, compressing the memory corresponding to an application in progress in the background of the electronic device; and executing the first application.
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