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公开(公告)号：US20200371745A1
公开(公告)日：2020-11-26
申请号：US16843199
申请日：2020-04-08
发明人： Seungwon LEE , Namhyung KIM , Hanmin PARK , Kiyoung CHOI
摘要： A processor-implemented method of processing neural network data includes: setting first limit data by performing a first operation based on first input data and weight data generated from weights included in a filter; comparing the first limit data with an intermediate result of a second operation performed based on second input data and the weight data; and determining whether to perform a subsequent second operation based on a result of the comparing.
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公开(公告)号：US20220164164A1
公开(公告)日：2022-05-26
申请号：US17356771
申请日：2021-06-24
发明人： Hyung-Dal KWON , Ho Young KIM , Hanmin PARK , Jaehyeong SIM , Seung Wook LEE , Jae-Eon JO
摘要： An apparatus with deep learning includes: a systolic adder tree including adder trees connected in row and column directions; and an input multiplexer connected to an input register of at least one of the adder trees and configured to determine column directional data movement between the adder trees based on operation modes.
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公开(公告)号：US20220083390A1
公开(公告)日：2022-03-17
申请号：US17223139
申请日：2021-04-06
发明人： Jae-Eon JO , Hyung-Dal KWON , Hanmin PARK , Jaehyeong SIM , Seung Wook LEE
IPC分类号： G06F9/50 , G06N3/04 , G06N3/063 , G06F9/48 , G06F1/3237
摘要： A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.
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公开(公告)号：US20220035629A1
公开(公告)日：2022-02-03
申请号：US17102884
申请日：2020-11-24
发明人： Hyung-Dal KWON , Hanmin PARK , Seungwook LEE , Jae-Eon JO
摘要： Disclosed is an apparatus and method for performing deep learning operations. The apparatus includes a systolic array comprising multiplier accumulator (MAC) units, and a control circuit configured to control an operation of a multiplexer connected to at least one of the MAC units and operations of the MAC units according to a plurality of operation modes.
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5.发明公开公开(公告)号：US20240004809A1
公开(公告)日：2024-01-04
申请号：US18364872
申请日：2023-08-03
发明人： Hanmin PARK , Hyung-Dal KWON , Jaehyeong SIM , Seungwook LEE , Jae-Eon JO
CPC分类号： G06F13/1668 , G06N3/04
摘要： An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.
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公开(公告)号：US20220188070A1
公开(公告)日：2022-06-16
申请号：US17689454
申请日：2022-03-08
发明人： Seungwon LEE , Namhyung KIM , Hanmin PARK , Kiyoung CHOI
摘要： A processor-implemented method of processing neural network data includes: setting first limit data by performing a first operation based on first input data and weight data generated from weights included in a filter; comparing the first limit data with an intermediate result of a second operation performed based on second input data and the weight data; and determining whether to perform a subsequent second operation based on a result of the comparing.
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7.发明申请公开(公告)号：US20220066960A1
公开(公告)日：2022-03-03
申请号：US17182439
申请日：2021-02-23
发明人： Hanmin PARK , Hyung-Dal KWON , Jaehyeong SIM , Seungwook LEE , Jae-Eon JO
摘要： An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.
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8.发明申请公开(公告)号：US20200065659A1
公开(公告)日：2020-02-27
申请号：US16550498
申请日：2019-08-26
发明人： Seungwon LEE , Hanmin PARK , Gunhee LEE , Namhyung KIM , Joonsang YU , Kiyoung CHOI
摘要： A method of accelerating a training process of a neural network includes acquiring activations used in the training process and a bit-vector corresponding to the activations, selecting activations requiring an operation from among the acquired activations by using the bit-vector, and performing backward propagation using the selected activations and filters corresponding to the selected activations.
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