公开(公告)号：US20200227315A1

公开(公告)日：2020-07-16

申请号：US16564688

申请日：2019-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Sung PARK ,  Jong Hyuk PARK ,  Jin Woo BAE ,  Bo Un YOON ,  II Young YOON ,  Bong Sik CHOI

IPC: H01L21/768 ,  H01L21/027

Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

公开(公告)号：US20210242215A1

公开(公告)日：2021-08-05

申请号：US17237195

申请日：2021-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Sung PARK ,  Jong Hyuk PARK ,  Jin Woo BAE ,  Bo Un YOON ,  Il Young YOON ,  Bong Sik CHOI

IPC: H01L27/108 ,  H01L21/027 ,  H01L21/768 ,  H01L23/544

Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

公开(公告)号：US20140049187A1

公开(公告)日：2014-02-20

申请号：US14056912

申请日：2013-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Sung KIM ,  Kyu Cheol KANG ,  Jin Woo BAE ,  Choul Ho LEE ,  Jong Yang CHOO

IPC: H05B33/08 ,  H05B33/10 ,  F21V23/02

CPC classification number: H05B33/0893 ,  F21V23/02 ,  H05B33/0854 ,  H05B33/10 ,  H05B37/02 ,  Y10T29/49004

Abstract: A method of manufacturing a power supply unit (PSU) is provided. The method includes providing at least one PSU supplying a dimming signal to at least one light source, performing a first test for electrical characteristics of the at least one PSU, detecting light emitted from the at least one light source, measuring a flicker of the at least one light source, and performing a second test for a state of the at least one PSU based on a flicker measurement result, and packing a PSU determined to be in a normal state among the at least one PSU, as a result of the first test and the second test.

Abstract translation: 提供一种制造电源单元（PSU）的方法。 该方法包括：向至少一个光源提供至少一个提供调光信号的PSU，对所述至少一个PSU的电特性执行第一测试，检测从所述至少一个光源发射的光，测量所述至少一个光源的闪烁 至少一个光源，并且基于闪烁测量结果对所述至少一个PSU的状态执行第二测试，并且将所述至少一个PSU中确定为处于正常状态的PSU进行打包，作为所述第一 测试和第二次测试。