Abstract:
A three-dimensional image sensor includes a first photoelectric converter in a first pixel region of a substrate, a second photoelectric converter in a second pixel region of the substrate, a first transfer gate structure disposed on the substrate at one side of the first photoelectric converter, a second transfer gate structure and a drain gate structure disposed on the substrate at opposite sides of the second photoelectric converter and whose gate insulating layers are thinner the gate insulating layer of the first transfer gate structure. The gate insulating layers can be fabricated by forming a first insulating layer on the pixel regions of the substrate, removing part of the first insulating layer from the second pixel region, and subsequently forming a second insulating layer on the substrate including over a part of the first insulating layer which remains on the first pixel region.
Abstract:
An image sensor of reduced chip size includes a semiconductor substrate having an active pixel region in which a plurality of active pixels are disposed and a power delivery region in which a pad is disposed. A plurality of first transparent electrode layers is disposed over the semiconductor substrate, respectively corresponding to the plurality of active pixels. A second transparent electrode layer is integrally formed across the active pixels. An organic photoelectric layer is disposed between the plurality of first transparent electrode layers and the second transparent electrode layer. An interconnection layer is located at a level that is the same as or higher than an upper surface of the pad with respect to an upper main surface of the semiconductor substrate. The interconnection layer extends from the pad to the second transparent electrode layer, and includes a connector electrically connecting the pad and the second transparent electrode layer.
Abstract:
An image sensor of reduced chip size includes a semiconductor substrate having an active pixel region in which a plurality of active pixels are disposed and a power delivery region in which a pad is disposed. A plurality of first transparent electrode layers is disposed over the semiconductor substrate, respectively corresponding to the plurality of active pixels. A second transparent electrode layer is integrally formed across the active pixels. An organic photoelectric layer is disposed between the plurality of first transparent electrode layers and the second transparent electrode layer. An interconnection layer is located at a level that is the same as or higher than an upper surface of the pad with respect to an upper main surface of the semiconductor substrate. The interconnection layer extends from the pad to the second transparent electrode layer, and includes a connector electrically connecting the pad and the second transparent electrode layer.