公开(公告)号：US20230019217A1

公开(公告)日：2023-01-19

申请号：US17709790

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tackhwi LEE ,  Jaeduk LEE ,  Hojun LEE ,  Seongpil CHANG

IPC: H01L27/112 ,  G11C16/08 ,  G11C16/12

Abstract: A non-volatile memory device comprises a memory cell region including a plurality of cell transistors, a first-type semiconductor substrate including a peripheral circuit region including circuits configured to control the plurality of cell transistors, and a plurality of pass transistors on the peripheral circuit region of the semiconductor substrate, wherein the peripheral circuit region includes a first region and a second region which are doped to a depth at an upper portion of the semiconductor substrate while being insulated from each other by an implant region, wherein the first region is a second type different from the first type, and includes a first doped region, and a first well region beneath the first doped region and configured to have a higher doping concentration than the first doped region, wherein the second region is the first type, and includes a second doped region, and a second well region beneath the second doped region and configured to have a higher doping concentration than the second doped region, wherein a first pass transistor on the first region from among the plurality of pass transistors is connected to a string selection line or a ground selection transistor, wherein a second pass transistor on the second region from among the plurality of pass transistors is connected to a word line, wherein a positive voltage or a negative voltage is configured to be applied to the second well region during operation of the second pass transistor.

公开(公告)号：US20240130133A1

公开(公告)日：2024-04-18

申请号：US18446911

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon LEE ,  Seongpil CHANG ,  Sea Hoon LEE ,  Jaeduk LEE ,  Tackhwi LEE

IPC: H10B43/40 ,  H01L23/528 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

Abstract: A vertical nonvolatile memory device may include a peripheral circuit portion including a memory cell driving circuit and connection wiring; a first hydrogen diffusion barrier layer above the peripheral circuit portion; a first insulating layer above the first hydrogen diffusion barrier layer; a common source line layer above the first insulating layer; a second hydrogen diffusion barrier layer above the first insulating layer; and a memory cell stack structure above the common source line layer and the second hydrogen diffusion barrier layer.

公开(公告)号：US20250008726A1

公开(公告)日：2025-01-02

申请号：US18514801

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Lib KIM ,  Jaeduk LEE ,  Sea Hoon LEE ,  Tackhwi LEE ,  Seongpil CHANG

IPC: H10B41/27 ,  H01L23/48 ,  H01L25/065 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first substrate; a wiring layer on the first substrate; a second substrate on the wiring layer and including a conductive material; a first horizontal conductive layer and a second horizontal conductive layer sequentially stacked on the second substrate and connected to the second substrate; a gate stacking structure including an interlayer insulating layer and a gate electrode alternately stacked on the second horizontal conductive layer; a channel structure passing through the gate stacking structure and connected to the second substrate; a first capacitor electrode on a same layer as the second substrate; a second capacitor electrode overlapping the first capacitor electrode; and a first dielectric layer between the first capacitor electrode and the second capacitor electrode, wherein the second capacitor electrode is on a same layer as at least one of the wiring layer, the second substrate, the first horizontal conductive layer, or the gate electrode.

公开(公告)号：US20240121952A1

公开(公告)日：2024-04-11

申请号：US18232568

申请日：2023-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sohyeon LEE ,  Seahoon LEE ,  Jaeduk LEE ,  Tackhwi LEE

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A vertical memory device includes a substrate, first and second sub-semiconductor patterns, first and second common source contacts, and first and second cell structures. The substrate includes a first region and a second region having a same length as the first region in a first direction, the first region having a first width in a second direction perpendicular to the first direction, and the second region having a second width in the second direction that is less than the first width. The first sub-semiconductor pattern covers the first region, and a portion of the first sub-semiconductor pattern has a first thickness. The second sub-semiconductor pattern covers the second region and has a second thickness that is less than the first thickness. The first and second common source contacts are disposed on edges in the second direction of the first and second patterns, respectively.