公开(公告)号：US20250089261A1

公开(公告)日：2025-03-13

申请号：US18739636

申请日：2024-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sea Hoon LEE ,  Jun Hee LIM ,  Jun Seok OH ,  Seong Pil CHANG

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A transistor that may provide improved durability and reliability is disclosed. The transistor includes a substrate including an active region, an element isolation film in the substrate that defines the active region, a first impurity region on a lower surface of the element isolation film, a second impurity region in the substrate, a gate electrode on the substrate and extending in a first direction, a source/drain area on at least one side of the gate electrode, a first source/drain contact group on the source/drain area, and a second source/drain contact group on the source/drain area and spaced apart from the first source/drain contact group in the first direction, wherein the second impurity region is between the first source/drain contact group and the second source/drain contact group.

公开(公告)号：US20250017008A1

公开(公告)日：2025-01-09

申请号：US18439835

申请日：2024-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang Lib KIM ,  Sungsu MOON ,  Sea Hoon LEE ,  Junhee LIM ,  Seongpil CHANG

IPC: H10B43/27 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a cell array region and a connection region. A gate stacking structure includes gate electrodes and interlayer insulation layers that are alternately stacked. The gate stacking structure extends in a first direction and is separated by separation structures in a second direction. A channel structure penetrates the gate stacking structure in the cell array region. Gate contact portions penetrate the gate stacking structure in the connection region. The gate contact portions are electrically connected to the gate electrodes, respectively. An insulation layer is provided separately from the separation structure and covers at least the gate stacking structure. The insulation layer comprises a base insulation portion and a hydrogen-containing insulation portion. The hydrogen-containing insulation portion includes a hydrogen-containing portion having a different material from a material of the base insulation portion. The hydrogen-containing portion including hydrogen.

公开(公告)号：US20250008726A1

公开(公告)日：2025-01-02

申请号：US18514801

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Lib KIM ,  Jaeduk LEE ,  Sea Hoon LEE ,  Tackhwi LEE ,  Seongpil CHANG

IPC: H10B41/27 ,  H01L23/48 ,  H01L25/065 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first substrate; a wiring layer on the first substrate; a second substrate on the wiring layer and including a conductive material; a first horizontal conductive layer and a second horizontal conductive layer sequentially stacked on the second substrate and connected to the second substrate; a gate stacking structure including an interlayer insulating layer and a gate electrode alternately stacked on the second horizontal conductive layer; a channel structure passing through the gate stacking structure and connected to the second substrate; a first capacitor electrode on a same layer as the second substrate; a second capacitor electrode overlapping the first capacitor electrode; and a first dielectric layer between the first capacitor electrode and the second capacitor electrode, wherein the second capacitor electrode is on a same layer as at least one of the wiring layer, the second substrate, the first horizontal conductive layer, or the gate electrode.

公开(公告)号：US20240431113A1

公开(公告)日：2024-12-26

申请号：US18529241

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Lib KIM ,  Sea Hoon LEE ,  Junhee LIM

IPC: H10B43/40 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a circuit region including a peripheral circuit on a substrate; and a cell region adjacent to the circuit region. The cell region includes a cell array region and a connecting region. The cell region also includes a gate stack that includes an interlayer insulating layer and a gate electrode, alternately stacked on the substrate; a channel in the cell array region that extends through the gate stack; a main support in the connecting region that extends through the gate stack; and a contact electrode in the connecting region connected to the gate electrode through the gate stack. The main support includes a first portion extending along a first direction; and a second portion extending from the first portion in a second direction crossing the first direction. At least a portion of the contact electrode is surrounded by the first and second portions of the main support.

公开(公告)号：US20240130133A1

公开(公告)日：2024-04-18

申请号：US18446911

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon LEE ,  Seongpil CHANG ,  Sea Hoon LEE ,  Jaeduk LEE ,  Tackhwi LEE

IPC: H10B43/40 ,  H01L23/528 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

Abstract: A vertical nonvolatile memory device may include a peripheral circuit portion including a memory cell driving circuit and connection wiring; a first hydrogen diffusion barrier layer above the peripheral circuit portion; a first insulating layer above the first hydrogen diffusion barrier layer; a common source line layer above the first insulating layer; a second hydrogen diffusion barrier layer above the first insulating layer; and a memory cell stack structure above the common source line layer and the second hydrogen diffusion barrier layer.