公开(公告)号：US11164636B2

公开(公告)日：2021-11-02

申请号：US16898533

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyeong Lee ,  Kyungmoon Kim ,  Woojae Jang ,  Chanjong Ju

IPC: G11C7/00 ,  G11C16/16 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/34 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

Abstract: A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.

公开(公告)号：US10699789B2

公开(公告)日：2020-06-30

申请号：US16177479

申请日：2018-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyeong Lee ,  Kyungmoon Kim ,  Woojae Jang ,  Chanjong Ju

IPC: G11C7/00 ,  G11C16/16 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/34 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

Abstract: A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.

公开(公告)号：US20250166715A1

公开(公告)日：2025-05-22

申请号：US18916863

申请日：2024-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyeon Han ,  Jinkyu Kang ,  Woojae Jang

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10

Abstract: A memory device includes a plurality of memory cells configured to store at least one bit, the memory device comprising a first wordline and a second wordline. The memory device is configured to perform a first programming operation on the first wordline on a plurality of memory cells in a higher state, the higher state referring to a state in which the plurality of memory cells have threshold voltages above a particular voltage; perform a second programming operation on the second wordline; and perform a third programming operation with a voltage lower than a voltage of the first programming operation when the second programming operation is performed after the first programming operation is performed.

公开(公告)号：US11699490B2

公开(公告)日：2023-07-11

申请号：US17220218

申请日：2021-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soyeong Gwak ,  Raeyoung Lee ,  Jinkyu Kang ,  Sejun Park ,  Changhwan Shin ,  Jaeduk Lee ,  Woojae Jang

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/16 ,  G11C7/106 ,  G11C7/1087 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/349

Abstract: An operating method of a storage device includes reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device; selecting an operation mode corresponding to the read wear-out pattern using the controller; and transmitting the selected operation mode to the non-volatile memory device using the controller.

公开(公告)号：US11257841B2

公开(公告)日：2022-02-22

申请号：US16787195

申请日：2020-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Kyu Kang ,  Woojae Jang ,  Changsub Lee ,  Sejun Park ,  Jaeduk Lee ,  Jung Hoon Lee

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/423 ,  H01L29/78

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.