公开(公告)号：US10134980B2

公开(公告)日：2018-11-20

申请号：US15675089

申请日：2017-08-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jong-Chul Park ,  Byoung-Jae Bae ,  Shin-Jae Kang ,  Young-Seok Choi

IPC分类号： H01L29/82 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

摘要： In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.

公开(公告)号：US09735349B2

公开(公告)日：2017-08-15

申请号：US14612323

申请日：2015-02-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jong-Chul Park ,  Byoung-Jae Bae ,  Shin-Jae Kang ,  Young-Seok Choi

IPC分类号： H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

摘要： In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.

公开(公告)号：US09698198B2

公开(公告)日：2017-07-04

申请号：US14602490

申请日：2015-01-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Young-Seok Choi ,  Jaehun Seo ,  Hyun-woo Yang ,  Jongchul Park

IPC分类号： H01L29/66 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： Provided is a memory device, including a memory element on a substrate; a protection insulating pattern covering a side surface of the memory element and exposing a top surface of the memory element; an upper mold layer on the protection insulating pattern; and a bit line on and connected to the memory element, the bit line extending in a first direction, the protection insulating pattern including a first protection insulating pattern covering a lower side surface of the memory element; and a second protection insulating pattern covering an upper side surface of the memory element and including a different material from the first protection insulating pattern.

公开(公告)号：US09159729B2

公开(公告)日：2015-10-13

申请号：US14028976

申请日：2013-09-17

申请人： Samsung Electronics Co., Ltd.

发明人： Hyongsoo Kim ,  Jin-Su Lee ,  Hojun Kwon ,  Dongkyun Park ,  Jiseung Lee ,  Young-Seok Choi

IPC分类号： H01L27/108 ,  H01L49/02

CPC分类号： H01L27/10817 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/91

摘要： Capacitor of a semiconductor device, and a method of fabricating the same, include sequentially forming a mold structure and a polysilicon pattern over a semiconductor substrate, patterning the mold structure using the polysilicon pattern as an etch mask to form lower electrode holes penetrating the mold structure, forming a protection layer covering a surface of the polysilicon pattern, forming lower electrodes in the lower electrode holes provided with the protection layer, removing the polysilicon pattern and the protection layer to expose upper sidewalls of the lower electrodes, removing the mold structure to expose lower sidewalls of the lower electrodes, and sequentially forming a dielectric and an upper electrode covering the lower electrodes.

摘要翻译： 半导体器件的电容器及其制造方法包括在半导体衬底上顺序地形成模具结构和多晶硅图案，使用多晶硅图案将模具结构图案化为蚀刻掩模，以形成贯穿模具结构的下部电极孔 形成覆盖多晶硅图案的表面的保护层，在设置有保护层的下电极孔中形成下电极，去除多晶硅图案和保护层以暴露下电极的上侧壁，去除模具结构暴露 下电极的下侧壁，并且依次形成覆盖下电极的电介质和上电极。