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公开(公告)号：US11881482B2
公开(公告)日：2024-01-23
申请号：US17852040
申请日：2022-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gihee Cho , Sanghyuck Ahn , Hyun-Suk Lee , Jungoo Kang , Jin-Su Lee , Hongsik Chae
CPC classification number: H01L27/101 , G11C8/14 , H01L28/60
Abstract: A semiconductor device includes; a bottom electrode on a substrate, a supporting pattern between the bottom electrode and an adjacent bottom electrode, a top electrode covering the bottom electrode and the supporting pattern, and a dielectric layer between the bottom electrode and the top electrode and between the supporting pattern and the top electrode. The bottom electrode may include a first portion including a seam and a second portion on the first portion, a top end of the second portion may be disposed at a height lower than an upper surface of the supporting pattern, and a portion of a bottom end of the second portion may be exposed to the seam.
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公开(公告)号：US20230217647A1
公开(公告)日：2023-07-06
申请号：US17952386
申请日：2022-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hongsik CHAE , Taekyun Kim , Jin-Su Lee , Hyo-Sun Min , Hyungsuk Jung , Jaehyoung Choi , Donguk Han
IPC: H01L27/108 , H01L49/02
CPC classification number: H01L27/10814 , H01L28/90
Abstract: A semiconductor device includes bottom electrodes on a substrate. A supporting pattern is disposed between the bottom electrodes in a plan view. A top electrode covers the bottom electrodes and the supporting pattern. A dielectric layer is disposed between the bottom electrodes and the top electrode and between the supporting pattern and the top electrode. A capping pattern is interposed between the bottom electrodes and the dielectric layer and between the supporting pattern and the dielectric layer. The capping pattern covers at least a portion of a side surface of the supporting pattern and extends to cover a top surface of the supporting pattern and top surfaces of the bottom electrodes.
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公开(公告)号：US11812601B2
公开(公告)日：2023-11-07
申请号：US17220411
申请日：2021-04-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jun Goo Kang , Sang Hyuck Ahn , Sang Yeol Kang , Jin-Su Lee , Hyun-Suk Lee , Gi Hee Cho , Hong Sik Chae
Abstract: A semiconductor device includes a substrate, first and second supporter patterns stacked sequentially on the substrate in a first direction and spaced apart from an upper surface of the substrate, a lower electrode hole that extends through the first and second supporter patterns on the substrate in the first direction, an interface film on side walls and a bottom surface of the lower electrode hole, a lower electrode inside of the lower electrode hole on the interface film, a capacitor dielectric film that is in physical contact with side walls of the interface film, an uppermost surface of the interface film, and an uppermost surface of the lower electrode, the uppermost surface of the interface film is formed on a same plane as an upper surface of the second supporter pattern.
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4.发明申请MIM Capacitors with Diffusion-Blocking Electrode Structures and Semiconductor Devices Including the Same 有权具有扩散阻挡电极结构的MIM电容器和包括其的半导体器件公开(公告)号：US20150061074A1
公开(公告)日：2015-03-05
申请号：US14340923
申请日：2014-07-25
Applicant: Samsung ELectronics Co., Ltd.
Inventor： Hyun-Suk Lee , Tae-Kyun Kim , Jin-Su Lee , Dong-Kyun Park , Jong-Myeong Lee
IPC: H01L49/02 , H01L27/108
CPC classification number: H01L28/75 , H01L27/1085 , H01L28/90
Abstract: A semiconductor device includes a MIM capacitor on a substrate. The MIM capacitor includes a dielectric region and first and second electrodes on opposite sides of the dielectric region. At least one of the first and second electrodes, e.g., an upper electrode, includes an oxygen diffusion blocking material, e.g., oxygen atoms, at a concentration that decreases in a direction away from the dielectric region. The at least one of the first and second electrodes may include a first layer having a first concentration of the oxygen diffusion blocking material and a second layer on the first layer and having a second concentration of the oxygen diffusion blocking material less than the first concentration. The at least one of the first and second electrodes may further include a third layer on the second layer and having a concentration of the oxygen diffusion blocking material less than the second concentration.
Abstract translation: 半导体器件在衬底上包括MIM电容器。 MIM电容器包括电介质区域和在电介质区域的相对侧上的第一和第二电极。 第一电极和第二电极中的至少一个，例如上电极，包括氧离子阻挡材料，例如氧原子，其浓度在远离电介质区域的方向上减小。 第一和第二电极中的至少一个可以包括具有第一浓度的氧扩散阻挡材料的第一层和第一层上的第二层，并且具有小于第一浓度的第二浓度的氧扩散阻挡材料。 第一和第二电极中的至少一个还可以包括第二层上的第三层，并且具有小于第二浓度的氧扩散阻塞材料的浓度。
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公开(公告)号：US09673272B2
公开(公告)日：2017-06-06
申请号：US14863820
申请日：2015-09-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yunjung Choi , Se Hoon Oh , Jin-Su Lee , Younsoo Kim , HanJin Lim
Abstract: A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode.
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Patent Agency Ranking
6.发明授权MIM capacitors with diffusion-blocking electrode structures and semiconductor devices including the same 有权具有扩散阻挡电极结构的MIM电容器和包括其的半导体器件公开(公告)号：US09520460B2
公开(公告)日：2016-12-13
申请号：US14340923
申请日：2014-07-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Suk Lee , Tae-Kyun Kim , Jin-Su Lee , Dong-Kyun Park , Jong-Myeong Lee
IPC: H01L49/02 , H01L27/108
CPC classification number: H01L28/75 , H01L27/1085 , H01L28/90
Abstract: A semiconductor device includes a MIM capacitor on a substrate. The MIM capacitor includes a dielectric region and first and second electrodes on opposite sides of the dielectric region. At least one of the first and second electrodes, e.g., an upper electrode, includes an oxygen diffusion blocking material, e.g., oxygen atoms, at a concentration that decreases in a direction away from the dielectric region. The at least one of the first and second electrodes may include a first layer having a first concentration of the oxygen diffusion blocking material and a second layer on the first layer and having a second concentration of the oxygen diffusion blocking material less than the first concentration. The at least one of the first and second electrodes may further include a third layer on the second layer and having a concentration of the oxygen diffusion blocking material less than the second concentration.
Abstract translation: 半导体器件在衬底上包括MIM电容器。 MIM电容器包括电介质区域和在电介质区域的相对侧上的第一和第二电极。 第一电极和第二电极中的至少一个，例如上电极，包括氧离子阻挡材料，例如氧原子，其浓度在远离电介质区域的方向上减小。 第一和第二电极中的至少一个可以包括具有第一浓度的氧扩散阻挡材料的第一层和第一层上的第二层，并且具有小于第一浓度的第二浓度的氧扩散阻塞材料。 第一和第二电极中的至少一个还可以包括第二层上的第三层，并且具有小于第二浓度的氧扩散阻塞材料的浓度。
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公开(公告)号：US09159729B2
公开(公告)日：2015-10-13
申请号：US14028976
申请日：2013-09-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyongsoo Kim , Jin-Su Lee , Hojun Kwon , Dongkyun Park , Jiseung Lee , Young-Seok Choi
IPC: H01L27/108 , H01L49/02
CPC classification number: H01L27/10817 , H01L27/10852 , H01L28/40 , H01L28/91
Abstract: Capacitor of a semiconductor device, and a method of fabricating the same, include sequentially forming a mold structure and a polysilicon pattern over a semiconductor substrate, patterning the mold structure using the polysilicon pattern as an etch mask to form lower electrode holes penetrating the mold structure, forming a protection layer covering a surface of the polysilicon pattern, forming lower electrodes in the lower electrode holes provided with the protection layer, removing the polysilicon pattern and the protection layer to expose upper sidewalls of the lower electrodes, removing the mold structure to expose lower sidewalls of the lower electrodes, and sequentially forming a dielectric and an upper electrode covering the lower electrodes.
Abstract translation: 半导体器件的电容器及其制造方法包括在半导体衬底上顺序地形成模具结构和多晶硅图案，使用多晶硅图案将模具结构图案化为蚀刻掩模，以形成贯穿模具结构的下部电极孔 形成覆盖多晶硅图案的表面的保护层，在设置有保护层的下电极孔中形成下电极，去除多晶硅图案和保护层以暴露下电极的上侧壁，去除模具结构暴露 下电极的下侧壁，并且依次形成覆盖下电极的电介质和上电极。
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公开(公告)号：US12205952B2
公开(公告)日：2025-01-21
申请号：US18539062
申请日：2023-12-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gihee Cho , Sanghyuck Ahn , Hyun-Suk Lee , Jungoo Kang , Jin-Su Lee , Hongsik Chae
Abstract: A semiconductor device includes; a bottom electrode on a substrate, a supporting pattern between the bottom electrode and an adjacent bottom electrode, a top electrode covering the bottom electrode and the supporting pattern, and a dielectric layer between the bottom electrode and the top electrode and between the supporting pattern and the top electrode. The bottom electrode may include a first portion including a seam and a second portion on the first portion, a top end of the second portion may be disposed at a height lower than an upper surface of the supporting pattern, and a portion of a bottom end of the second portion may be exposed to the seam.
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公开(公告)号：US12119374B2
公开(公告)日：2024-10-15
申请号：US17857383
申请日：2022-07-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gihee Cho , Sangyeol Kang , Jungoo Kang , Taekyun Kim , Jiwoon Park , Sanghyuck Ahn , Jin-Su Lee , Hyun-Suk Lee , Hongsik Chae
CPC classification number: H01L28/92 , H10B12/0335 , H10B12/053 , H10B12/315 , H10B12/34 , H10B12/482 , H10B12/488
Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.
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公开(公告)号：US20220037325A1
公开(公告)日：2022-02-03
申请号：US17220411
申请日：2021-04-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jun Goo Kang , Sang Hyuck Ahn , Sang Yeol Kang , Jin-Su Lee , Hyun-Suk Lee , Gi Hee Cho , Hong Sik Chae
IPC: H01L27/108 , H01L49/02
Abstract: A semiconductor device includes a substrate, first and second supporter patterns stacked sequentially on the substrate in a first direction and spaced apart from an upper surface of the substrate, a lower electrode hole that extends through the first and second supporter patterns on the substrate in the first direction, an interface film on side walls and a bottom surface of the lower electrode hole, a lower electrode inside of the lower electrode hole on the interface film, a capacitor dielectric film that is in physical contact with side walls of the interface film, an uppermost surface of the interface film, and an uppermost surface of the lower electrode, the uppermost surface of the interface film is formed on a same plane as an upper surface of the second supporter pattern.
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