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1.发明申请公开(公告)号：US20200220077A1
公开(公告)日：2020-07-09
申请号：US16824927
申请日：2020-03-20
发明人： Shin-Jae Kang , Gyuhwan Oh , Jiyoon Chung , Junyeon Hwang
摘要： Variable resistance memory devices are provided. A variable resistance memory device includes conductive lines and a memory cell including a variable resistance element on one of the conductive lines. The variable resistance memory device includes a first insulating region between the conductive lines. Moreover, the variable resistance memory device includes a second insulating region on the first insulating region between the conductive lines. Methods of forming variable resistance memory devices are also provided.
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公开(公告)号：US20130164928A1
公开(公告)日：2013-06-27
申请号：US13775496
申请日：2013-02-25
发明人： Tai-Soo Lim , HyunSeok Lim , Shin-Jae Kang , Kyung-Tae Jang
IPC分类号： H01L21/28
CPC分类号： H01L27/11578 , H01L21/28556 , H01L21/76879 , H01L23/485 , H01L27/11582 , H01L27/24 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L45/04 , H01L45/145 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.
摘要翻译： 形成半导体器件的方法包括在半导体结构上形成绝缘层，在绝缘层中形成开口，该开口具有由绝缘层的一侧限定的侧壁，在开口中形成第一金属层，至少部分地 通过对第一金属层进行湿蚀刻工艺，并且在蚀刻的第一金属层上选择性地形成第二金属层，使开口的侧壁暴露。 第一金属层的平均粒径小于第二金属层的平均粒径。 还公开了相关的半导体器件。
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公开(公告)号：US09735349B2
公开(公告)日：2017-08-15
申请号：US14612323
申请日：2015-02-03
发明人： Jong-Chul Park , Byoung-Jae Bae , Shin-Jae Kang , Young-Seok Choi
CPC分类号： H01L43/12 , G11C11/161 , H01L27/228 , H01L43/08
摘要： In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.
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公开(公告)号：US11840760B2
公开(公告)日：2023-12-12
申请号：US16207967
申请日：2018-12-03
发明人： Shin-Jae Kang , Dong-Hoon Han , Do-Hyung Kim , Kyung-Wook Park , Kevin Bae , Sun-Soo Lee , In-Jae Lee , Jeon-Il Lee , Chae-Mook Lim
IPC分类号： C23C16/455 , H01L21/768 , H01L21/285 , C23C16/34
CPC分类号： C23C16/45544 , C23C16/34 , C23C16/45561 , H01L21/28562 , H01L21/76843
摘要： In a layer deposition method, a substrate is loaded into a process chamber. A gas filling tank is charged with a gas to a predetermined charge pressure. The pressure of the gas is elevated to a pressure greater than the predetermined charge pressure. The gas is introduced into the process chamber.
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公开(公告)号：US10134980B2
公开(公告)日：2018-11-20
申请号：US15675089
申请日：2017-08-11
发明人： Jong-Chul Park , Byoung-Jae Bae , Shin-Jae Kang , Young-Seok Choi
摘要： In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.
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6.发明授权公开(公告)号：US11127900B2
公开(公告)日：2021-09-21
申请号：US16824927
申请日：2020-03-20
发明人： Shin-Jae Kang , Gyuhwan Oh , Jiyoon Chung , Junyeon Hwang
摘要： Variable resistance memory devices are provided. A variable resistance memory device includes conductive lines and a memory cell including a variable resistance element on one of the conductive lines. The variable resistance memory device includes a first insulating region between the conductive lines. Moreover, the variable resistance memory device includes a second insulating region on the first insulating region between the conductive lines. Methods of forming variable resistance memory devices are also provided.
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7.发明授权公开(公告)号：US10720577B2
公开(公告)日：2020-07-21
申请号：US15862133
申请日：2018-01-04
发明人： Shin-Jae Kang , Gyuhwan Oh , Jiyoon Chung , Junyeon Hwang
摘要： Variable resistance memory devices are provided. A variable resistance memory device includes conductive lines and a memory cell including a variable resistance element on one of the conductive lines. The variable resistance memory device includes a first insulating region between the conductive lines. Moreover, the variable resistance memory device includes a second insulating region on the first insulating region between the conductive lines. Methods of forming variable resistance memory devices are also provided.
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8.发明申请公开(公告)号：US20190067569A1
公开(公告)日：2019-02-28
申请号：US15862133
申请日：2018-01-04
发明人： Shin-Jae Kang , Gyuhwan Oh , Jiyoon Chung , Junyeon Hwang
摘要： Variable resistance memory devices are provided. A variable resistance memory device includes conductive lines and a memory cell including a variable resistance element on one of the conductive lines. The variable resistance memory device includes a first insulating region between the conductive lines. Moreover, the variable resistance memory device includes a second insulating region on the first insulating region between the conductive lines. Methods of forming variable resistance memory devices are also provided.
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公开(公告)号：US08691682B2
公开(公告)日：2014-04-08
申请号：US13775496
申请日：2013-02-25
发明人： Tai-Soo Lim , HyunSeok Lim , Shin-Jae Kang , Kyung-Tae Jang
IPC分类号： H01L21/00
CPC分类号： H01L27/11578 , H01L21/28556 , H01L21/76879 , H01L23/485 , H01L27/11582 , H01L27/24 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L45/04 , H01L45/145 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.
摘要翻译： 形成半导体器件的方法包括在半导体结构上形成绝缘层，在绝缘层中形成开口，该开口具有由绝缘层的一侧限定的侧壁，在开口中形成第一金属层，至少部分地 通过对第一金属层进行湿蚀刻工艺，并且在蚀刻的第一金属层上选择性地形成第二金属层，使开口的侧壁暴露。 第一金属层的平均粒径小于第二金属层的平均粒径。 还公开了相关的半导体器件。
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