公开(公告)号：US09940271B2

公开(公告)日：2018-04-10

申请号：US15483695

申请日：2017-04-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Tuers ,  Abhijeet Manohar ,  Yoav Weinberg ,  Milton Lourenco Barrocas

IPC: G06F13/372 ,  G06F13/16 ,  G06F13/40 ,  G06F13/362 ,  G06F13/38

CPC classification number: G06F13/1689 ,  G06F13/1668 ,  G06F13/362 ,  G06F13/385 ,  G06F13/4068 ,  G11C7/22 ,  G11C16/32

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

公开(公告)号：US20170212849A1

公开(公告)日：2017-07-27

申请号：US15483695

申请日：2017-04-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Tuers ,  Abhijeet Manohar ,  Yoav Weinberg ,  Milton Lourenco Barrocas

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/1668 ,  G06F13/362 ,  G06F13/385 ,  G06F13/4068 ,  G11C7/22 ,  G11C16/32

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

公开(公告)号：US09620182B2

公开(公告)日：2017-04-11

申请号：US14145116

申请日：2013-12-31

Applicant: SanDisk Technologies LLC

Inventor： Daniel Tuers ,  Abhijeet Manohar ,  Yoav Weinberg ,  Milton Lourenco Barrocas

IPC: G06F13/372 ,  G11C7/22 ,  G11C16/32 ,  G06F13/362 ,  G06F13/38 ,  G06F13/16

CPC classification number: G06F13/1689 ,  G06F13/1668 ,  G06F13/362 ,  G06F13/385 ,  G06F13/4068 ,  G11C7/22 ,  G11C16/32

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.