公开(公告)号：US09213600B2

公开(公告)日：2015-12-15

申请号：US14092215

申请日：2013-11-27

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen ,  Yunxiang Wu ,  Alexander Hubris ,  Christopher Brewer

IPC: H03M13/11 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/45

Abstract: An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract translation: 一种装置包括一个或多个纠错解码器，缓冲器，至少一个直接存储器访问（DMA）引擎和至少一个处理器。 缓冲器可以被配置为存储要由一个或多个纠错解码器解码的数据。 至少一个DMA引擎可以耦合缓冲器和一个或多个纠错解码器。 可以使至少一个处理器能够向至少一个DMA引擎发送消息。 消息可以被配置为递送DMA控制信息和相应的数据路径控制信息。 可以基于DMA控制信息从缓冲器读取数据，并将其与相应的数据路径控制信息一起递送到一个或多个纠错解码器。 可以使一个或多个纠错解码器根据相应的数据路径控制信息解码从缓冲器读取的数据。

公开(公告)号：US09495244B2

公开(公告)日：2016-11-15

申请号：US14967933

申请日：2015-12-14

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen ,  Yunxiang Wu ,  Alexander Hubris ,  Christopher Brewer

IPC: H03M13/11 ,  G06F11/10 ,  G11C29/52 ,  H03M13/45

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/45

Abstract: An apparatus includes one or more error-correction decoders, a buffer, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one processor is generally enabled to send messages to the one or more error-correction decoders. The messages may contain datapath control information corresponding to data in the buffer to be decoded by the one or more error-correction decoders. The one or more error-correction decoders are generally enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract translation: 一种装置包括一个或多个纠错解码器，缓冲器和至少一个处理器。 缓冲器可以被配置为存储要由一个或多个纠错解码器解码的数据。 通常使能至少一个处理器来向一个或多个纠错解码器发送消息。 消息可以包含与要由一个或多个纠错解码器解码的缓冲器中的数据相对应的数据路径控制信息。 通常，一个或多个错误校正解码器能够根据相应的数据路径控制信息解码从缓冲器读取的数据。

公开(公告)号：US09459956B2

公开(公告)日：2016-10-04

申请号：US13958162

申请日：2013-08-02

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Alexander Hubris ,  Zhengang Chen ,  AbdelHakim S. Alhussien ,  YingQuan Wu

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

CPC classification number: G06F11/1048 ,  G06F11/10 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1142 ,  H03M13/116 ,  H03M13/1171 ,  H03M13/6561 ,  H03M13/658

Abstract: A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.

Abstract translation: 低密度奇偶校验解码器包括可变节点处理器，其可操作以生成可变节点以校验节点消息，并且基于对可变节点消息的校验节点来计算感知值;校验节点处理器，可操作以将校验节点生成到可变节点消息向量;以及 基于变量节点来计算校验和以检查节点消息;以及收敛检测器和位图生成器，其可操作用于感知值的收敛并生成至少一个位图，其识别连接到具有不满足奇偶校验检查的节点的变量节点 。

公开(公告)号：US20160098318A1

公开(公告)日：2016-04-07

申请号：US14967933

申请日：2015-12-14

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen ,  Yunxiang Wu ,  Alexander Hubris ,  Christopher Brewer

IPC: G06F11/10 ,  H03M13/45 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/45

Abstract: An apparatus includes one or more error-correction decoders, a buffer, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one processor is generally enabled to send messages to the one or more error-correction decoders. The messages may contain datapath control information corresponding to data in the buffer to be decoded by the one or more error-correction decoders. The one or more error-correction decoders are generally enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract translation: 一种装置包括一个或多个纠错解码器，缓冲器和至少一个处理器。 缓冲器可以被配置为存储要由一个或多个纠错解码器解码的数据。 通常使能至少一个处理器来向一个或多个纠错解码器发送消息。 消息可以包含与要由一个或多个纠错解码器解码的缓冲器中的数据相对应的数据路径控制信息。 通常，一个或多个错误校正解码器能够根据相应的数据路径控制信息解码从缓冲器读取的数据。