公开(公告)号：US09081666B2

公开(公告)日：2015-07-14

申请号：US13768215

申请日：2013-02-15

Applicant: Seagate Technology LLC

Inventor： Christopher Brewer ,  Earl T. Cohen

IPC: G06F13/00 ,  G06F12/02 ,  G06F13/16 ,  G11C5/04 ,  G06F9/38

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0688 ,  G06F9/38 ,  G06F12/0246 ,  G06F13/1694 ,  G06F13/385 ,  G11C5/04

Abstract: A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface. The non-volatile memory device interface may be configured to couple the system to one or more non-volatile memory devices. The micro-sequencer is generally coupled to (i) the control processor and (ii) the non-volatile memory device interface. The micro-sequencer includes a control store readable by the micro-sequencer and writable by the control processor. In response to receiving a particular one of the commands, the control processor is enabled to cause the micro-sequencer to begin executing at a location in the control store according to the particular command and the micro-sequencer is enabled to perform at least a portion of the particular command according to a protocol of the one or more non-volatile memory devices coupled to the non-volatile memory device interface.

Abstract translation: 系统包括控制处理器，非易失性存储器件接口和微定序器。 控制处理器可以被配置为经由命令接口接收命令并发送响应。 非易失性存储器设备接口可以被配置为将系统耦合到一个或多个非易失性存储器设备。 微定序器通常耦合到（i）控制处理器和（ii）非易失性存储器件接口。 微定序器包括可由微定序器读取并由控制处理器写入的控制存储器。 响应于接收到特定的一个命令，控制处理器能够使得微定序器根据特定命令开始在控制存储器中的一个位置执行，并且微定序器能够执行至少一部分 根据耦合到非易失性存储器设备接口的一个或多个非易失性存储器件的协议来执行特定命令。

公开(公告)号：US09213600B2

公开(公告)日：2015-12-15

申请号：US14092215

申请日：2013-11-27

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen ,  Yunxiang Wu ,  Alexander Hubris ,  Christopher Brewer

IPC: H03M13/11 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/45

Abstract: An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract translation: 一种装置包括一个或多个纠错解码器，缓冲器，至少一个直接存储器访问（DMA）引擎和至少一个处理器。 缓冲器可以被配置为存储要由一个或多个纠错解码器解码的数据。 至少一个DMA引擎可以耦合缓冲器和一个或多个纠错解码器。 可以使至少一个处理器能够向至少一个DMA引擎发送消息。 消息可以被配置为递送DMA控制信息和相应的数据路径控制信息。 可以基于DMA控制信息从缓冲器读取数据，并将其与相应的数据路径控制信息一起递送到一个或多个纠错解码器。 可以使一个或多个纠错解码器根据相应的数据路径控制信息解码从缓冲器读取的数据。

公开(公告)号：US09495244B2

公开(公告)日：2016-11-15

申请号：US14967933

申请日：2015-12-14

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen ,  Yunxiang Wu ,  Alexander Hubris ,  Christopher Brewer

IPC: H03M13/11 ,  G06F11/10 ,  G11C29/52 ,  H03M13/45

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/45

Abstract: An apparatus includes one or more error-correction decoders, a buffer, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one processor is generally enabled to send messages to the one or more error-correction decoders. The messages may contain datapath control information corresponding to data in the buffer to be decoded by the one or more error-correction decoders. The one or more error-correction decoders are generally enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract translation: 一种装置包括一个或多个纠错解码器，缓冲器和至少一个处理器。 缓冲器可以被配置为存储要由一个或多个纠错解码器解码的数据。 通常使能至少一个处理器来向一个或多个纠错解码器发送消息。 消息可以包含与要由一个或多个纠错解码器解码的缓冲器中的数据相对应的数据路径控制信息。 通常，一个或多个错误校正解码器能够根据相应的数据路径控制信息解码从缓冲器读取的数据。

公开(公告)号：US20160098318A1

公开(公告)日：2016-04-07

申请号：US14967933

申请日：2015-12-14

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen ,  Yunxiang Wu ,  Alexander Hubris ,  Christopher Brewer

IPC: G06F11/10 ,  H03M13/45 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/45

Abstract: An apparatus includes one or more error-correction decoders, a buffer, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one processor is generally enabled to send messages to the one or more error-correction decoders. The messages may contain datapath control information corresponding to data in the buffer to be decoded by the one or more error-correction decoders. The one or more error-correction decoders are generally enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract translation: 一种装置包括一个或多个纠错解码器，缓冲器和至少一个处理器。 缓冲器可以被配置为存储要由一个或多个纠错解码器解码的数据。 通常使能至少一个处理器来向一个或多个纠错解码器发送消息。 消息可以包含与要由一个或多个纠错解码器解码的缓冲器中的数据相对应的数据路径控制信息。 通常，一个或多个错误校正解码器能够根据相应的数据路径控制信息解码从缓冲器读取的数据。

公开(公告)号：US09262084B2

公开(公告)日：2016-02-16

申请号：US14729659

申请日：2015-06-03

Applicant: Seagate Technology LLC

Inventor： Christopher Brewer ,  Earl T. Cohen

IPC: G06F3/00 ,  G06F3/06 ,  G06F13/16 ,  G11C5/04 ,  G06F9/38 ,  G06F12/02 ,  G06F13/38

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0688 ,  G06F9/38 ,  G06F12/0246 ,  G06F13/1694 ,  G06F13/385 ,  G11C5/04

Abstract: An apparatus includes a device interface, a micro-sequencer, and a programmable sequence memory. The device interface may be configured to process a plurality of read/write operations to/from one or more non-volatile memory devices. The micro-sequencer may be configured to communicate with the device interface. The programmable sequence memory is generally readable by the micro-sequencer. In response to the apparatus receiving a command, (a) the micro-sequencer executes a set of instructions starting at a location in the programmable sequence memory according to the command and (b) the micro-sequencer is enabled to perform at least a portion of the command according to a protocol of the one or more non-volatile memory devices, when the one or more non-volatile memory devices are coupled to the device interface.

Abstract translation: 一种装置包括设备接口，微定序器和可编程顺序存储器。 设备接口可以被配置为处理来自一个或多个非易失性存储器设备的多个读/写操作。 微定序器可以被配置为与设备接口通信。 可编程序列存储器通常由微定序器读取。 响应于装置接收到命令，（a）微定序器根据该命令从可编程序存储器中的一个位置开始执行一组指令，并且（b）微定序器能够执行至少一部分 当所述一个或多个非易失性存储器设备耦合到所述设备接口时，根据所述一个或多个非易失性存储器设备的协议来执行所述命令。

公开(公告)号：US20150268870A1

公开(公告)日：2015-09-24

申请号：US14729659

申请日：2015-06-03

Applicant: Seagate Technology LLC

Inventor： Christopher Brewer ,  Earl T. Cohen

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0688 ,  G06F9/38 ,  G06F12/0246 ,  G06F13/1694 ,  G06F13/385 ,  G11C5/04

Abstract: An apparatus includes a device interface, a micro-sequencer, and a programmable sequence memory. The device interface may be configured to process a plurality of read/write operations to/from one or more non-volatile memory devices. The micro-sequencer may be configured to communicate with the device interface. The programmable sequence memory is generally readable by the micro-sequencer. In response to the apparatus receiving a command, (a) the micro-sequencer executes a set of instructions starting at a location in the programmable sequence memory according to the command and (b) the micro-sequencer is enabled to perform at least a portion of the command according to a protocol of the one or more non-volatile memory devices, when the one or more non-volatile memory devices are coupled to the device interface.

Abstract translation: 一种装置包括设备接口，微定序器和可编程顺序存储器。 设备接口可以被配置为处理来自一个或多个非易失性存储器设备的多个读/写操作。 微定序器可以被配置为与设备接口通信。 可编程序列存储器通常由微定序器读取。 响应于装置接收到命令，（a）微定序器根据该命令从可编程序存储器中的一个位置开始执行一组指令，并且（b）微定序器能够执行至少一部分 当所述一个或多个非易失性存储器设备耦合到所述设备接口时，根据所述一个或多个非易失性存储器设备的协议来执行所述命令。