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    Pixel, pixel array, and image sensor including the pixel array
    7.
    发明授权
    Pixel, pixel array, and image sensor including the pixel array 有权
    像素，像素阵列和包括像素阵列的图像传感器

    公开(公告)号：US08350217B2

    公开(公告)日：2013-01-08

    申请号：US13097752

    申请日：2011-04-29

    申请人： Seung Hoon Sa ,  Andrew Kunil Choe ,  Cheong Yong Park

    发明人： Seung Hoon Sa ,  Andrew Kunil Choe ,  Cheong Yong Park

    IPC分类号： G01J5/02

    CPC分类号： G01J3/513

    摘要： Disclosed are a pixel, a pixel array, and an image sensor including the pixel array. The pixel includes a first photo-sensing unit to detect a visible light and an IR, and a second photo-sensing unit provided at one side of the first photo-sensing unit to detect a light in which the IR is blocked.

    摘要翻译： 公开了像素，像素阵列和包括像素阵列的图像传感器。 像素包括用于检测可见光和IR的第一感光单元和设置在第一感光单元的一侧的第二感光单元，用于检测IR被阻挡的光。

    PIXEL, PIXEL ARRAY, AND IMAGE SENSOR INCLUDING THE PIXEL ARRAY
    8.
    发明申请
    PIXEL, PIXEL ARRAY, AND IMAGE SENSOR INCLUDING THE PIXEL ARRAY 有权
    像素，像素阵列和包含像素阵列的图像传感器

    公开(公告)号：US20120256090A1

    公开(公告)日：2012-10-11

    申请号：US13097752

    申请日：2011-04-29

    申请人： SEUNG HOON SA ,  Andrew Kunil Choe ,  Cheong Yong Park

    发明人： SEUNG HOON SA ,  Andrew Kunil Choe ,  Cheong Yong Park

    IPC分类号： G01J5/10

    CPC分类号： G01J3/513

    摘要： Disclosed are a pixel, a pixel array, and an image sensor including the pixel array. The pixel includes a first photo-sensing unit to detect a visible light and an IR, and a second photo-sensing unit provided at one side of the first photo-sensing unit to detect a light in which the IR is blocked.

    摘要翻译： 公开了像素，像素阵列和包括像素阵列的图像传感器。 像素包括用于检测可见光和IR的第一感光单元和设置在第一感光单元的一侧的第二感光单元，用于检测IR被阻挡的光。

    Digital-Analog Converter and Camera Module Having the Same
    9.
    发明申请
    Digital-Analog Converter and Camera Module Having the Same 有权
    数字模拟转换器和相机模块相同

    公开(公告)号：US20090140902A1

    公开(公告)日：2009-06-04

    申请号：US11997698

    申请日：2007-08-14

    申请人： Cheong Yong Park

    发明人： Cheong Yong Park

    IPC分类号： H03M1/68

    CPC分类号： H03M1/687 ,  H03M1/682 ,  H03M1/685 ,  H03M1/745 ,  H03M1/747

    摘要： Disclosed are a digital-analog converter and a camera module having the same. The digital-analog converter includes a plurality of decoders for receiving bits of a digital input signal by dividing the bits in a predetermined bit unit except for lower bits of the digital input signal, and decoding the bits into thermometer code signals, a delay unit for delaying output of the lower bits of the digital input signal, a latch unit for synchronizing output signals of the decoders with an output signal of the delay unit, and a current source for converting a digital signal output from the latch unit into an analog signal.

    摘要翻译： 公开了一种数模转换器和具有该数模转换器的相机模块。 数模转换器包括多个解码器，用于通过除了数字输入信号的较低位之外的预定位单元中的比特来接收数字输入信号的比特，并将比特解码为温度计代码信号，延迟单元 延迟数字输入信号的低位的输出，用于使解码器的输出信号与延迟单元的输出信号同步的锁存单元，以及用于将从锁存单元输出的数字信号转换为模拟信号的电流源。

    Digital-analog converter and camera module having the same
    10.
    发明授权
    Digital-analog converter and camera module having the same 有权
    数模转换器和具有相同功能的摄像模块

    公开(公告)号：US07746258B2

    公开(公告)日：2010-06-29

    申请号：US11997698

    申请日：2007-08-14

    申请人： Cheong Yong Park

    发明人： Cheong Yong Park

    IPC分类号： H03M1/66

    CPC分类号： H03M1/687 ,  H03M1/682 ,  H03M1/685 ,  H03M1/745 ,  H03M1/747

    摘要： Disclosed are a digital-analog converter and a camera module having the same. The digital-analog converter includes a plurality of decoders for receiving bits of a digital input signal by dividing the bits in a predetermined bit unit except for lower bits of the digital input signal, and decoding the bits into thermometer code signals, a delay unit for delaying output of the lower bits of the digital input signal, a latch unit for synchronizing output signals of the decoders with an output signal of the delay unit, and a current source for converting a digital signal output from the latch unit into an analog signal.

    摘要翻译： 公开了一种数模转换器和具有该数模转换器的相机模块。 数模转换器包括多个解码器，用于通过除了数字输入信号的较低位之外的预定位单元中的比特来接收数字输入信号的比特，并将比特解码为温度计代码信号，延迟单元 延迟数字输入信号的低位的输出，用于使解码器的输出信号与延迟单元的输出信号同步的锁存单元，以及用于将从锁存单元输出的数字信号转换为模拟信号的电流源。