公开(公告)号：US20240283121A1

公开(公告)日：2024-08-22

申请号：US18436391

申请日：2024-02-08

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi TANEDA ,  Yoko NAKABAYASHI ,  Noriyoshi SHIMIZU ,  Noritaka KATAGIRI ,  Tatsuki SUMI

IPC: H01P3/12 ,  H01P11/00

CPC classification number: H01P3/121 ,  H01P11/002

Abstract: A waveguide substrate includes a core substrate through which first through holes and second through holes are formed, a first conductive layer covering an inner wall of the first through holes and both sides of the core substrate, a second conductive layer covering an inner wall of the second through holes and both sides of the core substrate, a first filler material filling a space surrounded by the first conductive layer inside the first through holes, a second filler material filling a space surrounded by the second conductive layer inside the second through holes, and third conductive layers disposed on respective sides of the core substrate, the third conductive layers overlapping the first and second through holes in a plan view, and the third conductive layers being electrically connected to the first and second conductive layers, wherein the second conductive layer overlaps the first through holes in the plan view.

公开(公告)号：US20220399297A1

公开(公告)日：2022-12-15

申请号：US17833199

申请日：2022-06-06

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yoko NAKABAYASHI

IPC: H01L23/00 ,  H01L23/498

Abstract: A terminal structure includes a first wiring layer, an insulation layer covering the first wiring layer, an opening extending through the insulation layer and partially exposing the first wiring layer, a via wiring formed in the opening, a second wiring layer connected to the via wiring on the insulation layer, a protective metal layer on the second wiring layer, a solder layer covering the protective metal layer, and an intermetallic compound layer formed at an interface of the protective metal layer and the solder layer. The protective metal layer includes a projection projecting further outward from a side surface of the second wiring layer. The solder layer covers upper and side surfaces of the protective metal layer through the intermetallic compound layer and exposes a side surface of the second wiring layer. The intermetallic compound layer covers the upper and side surfaces of the protective metal layer.

公开(公告)号：US20240413063A1

公开(公告)日：2024-12-12

申请号：US18679656

申请日：2024-05-31

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Junichi NAKAMURA ,  Tomoya KITAMURA ,  Yoko NAKABAYASHI

IPC: H01L23/498 ,  H01L23/00 ,  H05K1/02 ,  H05K1/11

Abstract: A terminal structure includes a first wiring layer, an insulation layer covering the first wiring layer, an opening extending through the insulation layer, via wiring formed in the opening, a second wiring layer electrically connected to the via wiring on the insulation layer, a protective metal layer formed on the second wiring layer, a solder layer formed on the protective metal layer, and an intermetallic compound layer formed between the protective metal layer and the solder layer. The protective metal layer includes a projection projecting further outward from a side surface of the second wiring layer. The intermetallic compound layer covers only the upper surface of the protective metal layer. The solder layer covers only an upper surface of the intermetallic compound layer and exposes the side surfaces of the intermetallic compound layer, the protective metal layer, and the second wiring layer.

公开(公告)号：US20200013708A1

公开(公告)日：2020-01-09

申请号：US16449878

申请日：2019-06-24

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yoko NAKABAYASHI

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00

Abstract: A wiring substrate includes: a substrate; an oxide film including an oxide of one or both of Ti and Zr, the oxide film being formed on a surface of the substrate; an alloy film including an alloy of one or any combination of Ni, Co, and W with Cu, the alloy film being formed on the oxide film; and a Cu layer formed on the alloy film.

公开(公告)号：US20240332772A1

公开(公告)日：2024-10-03

申请号：US18526349

申请日：2023-12-01

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi TANEDA ,  Tatsuki SUMI ,  Yoko NAKABAYASHI

IPC: H01P3/12 ,  H01P11/00 ,  H05K1/02 ,  H05K3/46

CPC classification number: H01P3/121 ,  H01P3/122 ,  H01P11/002 ,  H05K1/0237 ,  H05K3/4682 ,  H05K2201/09985 ,  H05K2203/0723 ,  H05K2203/107

Abstract: A wiring board has a built-in post wall waveguide having a region surrounded by two mutually opposing conductors and first and second post walls connecting the two conductors and serving as a transmission path for electromagnetic waves. The conductors oppose each other with insulating layers interposed therebetween. The first post wall has first columnar portions, formed by a laminate of via interconnects penetrating the insulating layers, arranged at predetermined intervals in a first direction in which the electromagnetic waves are transmitted. The second post wall has second columnar portions similar to the first columnar portions. In a cross sectional view taken in a second direction perpendicular to the first direction, an interval between adjacent via interconnects in one of the insulating layers not in contact with the conductor is wider than an interval between adjacent via interconnects in two of the insulating layers in contact with the two conductors, respectively.

公开(公告)号：US20240006307A1

公开(公告)日：2024-01-04

申请号：US18341111

申请日：2023-06-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yoko NAKABAYASHI

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5226 ,  H01L23/5385 ,  H01L23/49827 ,  H01L23/5386

Abstract: An interconnect substrate includes alternately stacked pads and insulating layers, and via interconnects extending through respective ones of the insulating layers, the via interconnects and the pads being alternately stacked in a vertical direction, the pads being electrically connected to each other via the via interconnects, wherein the pads include a first pad disposed on an uppermost one of the insulating layers and electrically connectable to a semiconductor chip, the first pad being an uppermost layer pad, a second pad disposed on a second uppermost one of the insulating layers, and a third pad disposed on a third uppermost one of the insulating layers, and wherein the uppermost one of the insulating layers located between the first pad and the second pad is thicker the second uppermost one of the insulating layers located between the second pad and the third pad.