公开(公告)号：US20220157697A1

公开(公告)日：2022-05-19

申请号：US17526089

申请日：2021-11-15

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi TANEDA ,  Kei IMAFUJI ,  Yoshiki AKIYAMA ,  Kensuke UCHIDA

IPC: H01L23/498

Abstract: A wiring substrate includes a bendable portion including one or more wiring layers and insulation layers that are alternately stacked. The insulation layers of the bendable portion include a first insulation layer and a second insulation layer. The first insulation layer is located at an inner bent position of the bendable portion when the bendable portion is bent. The second insulation layer is located at an outer bent position of the bendable portion relative to the first insulation layer when the bendable portion is bent. The first insulation layer has a higher elastic modulus than the second insulation layer.

公开(公告)号：US20200092993A1

公开(公告)日：2020-03-19

申请号：US16554829

申请日：2019-08-29

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi TANEDA ,  Yukari CHINO

IPC: H05K1/02 ,  H05K3/42 ,  H05K1/18 ,  H05K1/11 ,  H05K3/46

Abstract: A wiring board includes a first interconnect layer, a first insulating layer covering the first interconnect layer, a second interconnect layer, thinner than the first interconnect layer, formed on the first insulating layer and having an interconnect density higher than that of the first interconnect layer, and a second insulating layer formed on the first insulating layer and covering the second interconnect layer. The first insulating layer includes a first layer including no reinforcing material, and a second layer including a reinforcing material. The first and second layers include a non-photosensitive thermosetting resin as a main component thereof. The first layer has a coefficient of thermal expansion higher than that of the second layer, and the second insulating layer includes a photosensitive resin as a main component thereof. The second interconnect layer includes an interconnect formed directly on and electrically connected to the first interconnect layer.

公开(公告)号：US20240283121A1

公开(公告)日：2024-08-22

申请号：US18436391

申请日：2024-02-08

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi TANEDA ,  Yoko NAKABAYASHI ,  Noriyoshi SHIMIZU ,  Noritaka KATAGIRI ,  Tatsuki SUMI

IPC: H01P3/12 ,  H01P11/00

CPC classification number: H01P3/121 ,  H01P11/002

Abstract: A waveguide substrate includes a core substrate through which first through holes and second through holes are formed, a first conductive layer covering an inner wall of the first through holes and both sides of the core substrate, a second conductive layer covering an inner wall of the second through holes and both sides of the core substrate, a first filler material filling a space surrounded by the first conductive layer inside the first through holes, a second filler material filling a space surrounded by the second conductive layer inside the second through holes, and third conductive layers disposed on respective sides of the core substrate, the third conductive layers overlapping the first and second through holes in a plan view, and the third conductive layers being electrically connected to the first and second conductive layers, wherein the second conductive layer overlaps the first through holes in the plan view.

公开(公告)号：US20220361340A1

公开(公告)日：2022-11-10

申请号：US17660701

申请日：2022-04-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi TANEDA ,  Noriyoshi SHIMIZU ,  Rie MIZUTANI ,  Masaya TAKIZAWA ,  Yoshiki AKIYAMA

IPC: H05K1/18 ,  H05K1/11

Abstract: A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.

公开(公告)号：US20240332772A1

公开(公告)日：2024-10-03

申请号：US18526349

申请日：2023-12-01

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi TANEDA ,  Tatsuki SUMI ,  Yoko NAKABAYASHI

IPC: H01P3/12 ,  H01P11/00 ,  H05K1/02 ,  H05K3/46

CPC classification number: H01P3/121 ,  H01P3/122 ,  H01P11/002 ,  H05K1/0237 ,  H05K3/4682 ,  H05K2201/09985 ,  H05K2203/0723 ,  H05K2203/107

Abstract: A wiring board has a built-in post wall waveguide having a region surrounded by two mutually opposing conductors and first and second post walls connecting the two conductors and serving as a transmission path for electromagnetic waves. The conductors oppose each other with insulating layers interposed therebetween. The first post wall has first columnar portions, formed by a laminate of via interconnects penetrating the insulating layers, arranged at predetermined intervals in a first direction in which the electromagnetic waves are transmitted. The second post wall has second columnar portions similar to the first columnar portions. In a cross sectional view taken in a second direction perpendicular to the first direction, an interval between adjacent via interconnects in one of the insulating layers not in contact with the conductor is wider than an interval between adjacent via interconnects in two of the insulating layers in contact with the two conductors, respectively.

公开(公告)号：US20230066839A1

公开(公告)日：2023-03-02

申请号：US17817110

申请日：2022-08-03

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi TANEDA ,  Noriyoshi SHIMIZU ,  Rie MIZUTANI ,  Masaya TAKIZAWA ,  Yoshiki AKIYAMA

IPC: H01L23/498 ,  H01L21/48

Abstract: A wiring board includes an interconnect structure including a plurality of interconnect layers, and a plurality of insulating layers having a photosensitive resin as a main component thereof, and an encapsulating resin layer having a non-photosensitive thermosetting resin as a main component thereof, laminated on an uppermost insulating layer of the plurality of insulating layers. An uppermost interconnect layer of the plurality of interconnect layers includes a pad protruding from the uppermost insulating layer. The encapsulating resin layer exposes an upper surface of the pad, and covers at least a portion of a side surface of the pad, and at least a portion of side surfaces of the plurality of insulating layers. The pad is configured to receive a semiconductor chip to be mounted thereon.

公开(公告)号：US20230054390A1

公开(公告)日：2023-02-23

申请号：US17817446

申请日：2022-08-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Rie MIZUTANI ,  Noriyoshi SHIMIZU ,  Hiroshi TANEDA ,  Masaya TAKIZAWA ,  Yoshiki AKIYAMA

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/46

Abstract: An interconnect substrate includes a core layer including a resin layer mainly composed of a non-photosensitive thermosetting resin and a through interconnect extending through the resin layer, the core layer having no reinforcement member contained therein, a first interconnect structure laminated on a first side of the core layer and including first interconnect layers and first insulating layers mainly composed of a photosensitive resin, and a second interconnect structure laminated on a second side of the core layer and including second interconnect layers and a single second insulating layer mainly composed of a photosensitive resin, wherein the first interconnect layers are electrically connected to the second interconnect layers via the through interconnect, wherein the core layer has greater rigidity than the first interconnect structure and the second interconnect structure, and wherein a thickness of the second interconnect structure is greater than a thickness of each of the first insulating layer.

公开(公告)号：US20220361331A1

公开(公告)日：2022-11-10

申请号：US17660700

申请日：2022-04-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Masaya TAKIZAWA ,  Rie MIZUTANI ,  Hiroshi TANEDA ,  Yoshiki AKIYAMA ,  Noriyoshi SHIMIZU

IPC: H05K1/11

Abstract: A wiring board includes a first interconnect structure including a first interconnect layer, and a first insulating layer including a non-photosensitive thermosetting resin as a main component thereof, a second interconnect structure including second interconnect layers, and second insulating layers including a photosensitive resin as a main component thereof, and laminated on the first interconnect structure, and an encapsulating resin layer including a non-photosensitive thermosetting resin as a main component thereof, and laminated on an uppermost second insulating layer. An uppermost second interconnect layer includes a pad protruding from the uppermost second insulating layer. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad. Thermal expansion coefficients of the first insulating layer and the encapsulating resin layer are lower than that of the second insulating layers.

公开(公告)号：US20190131236A1

公开(公告)日：2019-05-02

申请号：US16138252

申请日：2018-09-21

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Keigo SATO ,  Hiroshi TANEDA

IPC: H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L23/29 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes an interconnect substrate, an interconnect trace disposed on an upper surface of the interconnect substrate, a semiconductor chip mounted on the upper surface of the interconnect substrate, an adhesive resin layer disposed between the upper surface of the interconnect substrate and a lower surface of the semiconductor chip to bond the interconnect substrate and the semiconductor chip, the adhesive resin layer including an opening at a bottom of which an upper surface of the interconnect trace is situated, a barrier layer covering a sidewall of the opening, and conductive paste disposed inside the opening, wherein an electrode terminal of the semiconductor chip situated at the lower surface thereof is disposed inside the opening, with the conductive paste filling a space between the barrier layer and the electrode terminal.