CRYSTAL OSCILLATOR STARTUP TIME OPTIMIZATION

    公开(公告)号:US20200021244A1

    公开(公告)日:2020-01-16

    申请号:US16032348

    申请日:2018-07-11

    Abstract: An oscillation circuit including a crystal interface, a crystal amplifier, a level detector, a timing circuit, and a controller. When activated, the crystal amplifier drives a crystal coupled to the crystal interface to establish oscillation, and the level detector indicates when a target amplitude is detected. The controller activates the crystal amplifier and uses the timing circuit and the level detector to measure a startup time of oscillation. The measured startup time is used in calculating a wake up time from a sleep mode in time to perform an operation at a scheduled time. The startup time may be adjusted or averaged and may be remeasured with temperature change. A method of minimizing startup time of a crystal oscillator includes measuring startup time for determining a delay value for programming a wakeup circuit. Robust startup settings may be used in the event of startup failure due to a sleepy crystal.

    CRYSTAL DRIVER CIRCUIT WITH EXTERNAL OSCILLATION SIGNAL AMPLITUDE CONTROL

    公开(公告)号:US20190006990A1

    公开(公告)日:2019-01-03

    申请号:US15724714

    申请日:2017-10-04

    Abstract: A crystal driver integrated circuit with external oscillation signal amplitude control including an amplifier core, an input pin and an output pin, an adjustable capacitor, and a controller. The controller operates the amplifier core in any one of multiple operating modes including an oscillator mode and a bypass mode. During the bypass mode, the controller disables the amplifier core and adjusts the adjustable capacitor so that an amplitude of an oscillation signal received via the input pin from an external oscillator has a target amplitude. The external oscillation signal may be capacitively coupled for capacitive voltage division or directly coupled for impedance attenuation. An available voltage may be provided as a source voltage to the external oscillator via the output pin. An internal voltage regulator and/or switch may be included to re-provision the output pin to provide the source voltage during the bypass mode.

    CRYSTAL AMPLIFIER WITH RESISTIVE DEGENERATION

    公开(公告)号:US20190007005A1

    公开(公告)日:2019-01-03

    申请号:US15639137

    申请日:2017-06-30

    Inventor: TIAGO MARQUES

    Abstract: A crystal amplifier for driving a crystal to oscillate at a resonant frequency including a current source, an amplifier, and at least one degeneration resistor. The amplifier has an input coupled to an amplifier input node and has an amplifier output current path coupled the amplifier output node. Each degeneration resistor is coupled in series with the amplifier output current path. The current source provides a core bias current through the amplifier output current path and through each degeneration resistor to a reference node. The resistance of each degeneration resistor may be selected to minimize a frequency shift over an operating temperature range while maintaining at least one operating parameter within predetermined operating limits, or can be selected based on a crystal type. Each degeneration resistor may be fixed or adjustable.

    CRYSTAL DRIVER CIRCUIT CONFIGURABLE FOR DAISY CHAINING

    公开(公告)号:US20190006992A1

    公开(公告)日:2019-01-03

    申请号:US15645684

    申请日:2017-07-10

    Inventor: TIAGO MARQUES

    Abstract: A crystal driver integrated circuit configurable for daisy chaining including an amplifier core, an input pin and an output pin, and a controller that operates the amplifier core in any one of multiple operating modes. The operating modes include an oscillator mode for driving an external crystal coupled between the input and output pins to generate an oscillation signal at a target frequency, and an amplifier mode that amplifies an external oscillating signal provided to the input pin to provide an amplified oscillation signal on the output pin. The amplifier core includes a controllable current source that provides a core bias current to an amplifier having a level that is adjusted depending upon the operating mode and desired amplitude. The operating modes may include a bypass mode in which the amplifier core is disabled. The amplifier may be implemented as either an PMOS amplifier or an NMOS amplifier.

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