OSCILLATOR CIRCUIT, CHIP AND ELECTRONIC DEVICE

    公开(公告)号:US20240007051A1

    公开(公告)日:2024-01-04

    申请号:US18124859

    申请日:2023-03-22

    IPC分类号: H03B5/36 H03B5/06

    摘要: An oscillator circuit is provided and includes first and second terminals; an amplification circuit with an input end and an out end coupled to a first end and a second end of a crystal circuit through the first terminal and the second terminal, respectively; a gain control circuit coupled to the amplification circuit and including a differential amplifier, a first current source, a feedback path and a current mirror, wherein: the differential amplifier includes first and second transistors, sources of the first and second transistors are coupled to the first current source; a gate of the first transistor is coupled to a first direct current voltage and coupled to the input end or the output end through the feedback path; a gate of the second transistor is coupled to a second direct current voltage; the current mirror mirrors a current flowing through the second transistor to the amplification circuit.

    CIRCUIT AND METHOD FOR FACILITATING STARTUP TIME OF CRYSTAL OSCILLATOR

    公开(公告)号:US20190199288A1

    公开(公告)日:2019-06-27

    申请号:US15853942

    申请日:2017-12-25

    IPC分类号: H03B5/36 H03B29/00

    摘要: Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some embodiments, an adjustment block may be employed to adjust the count determined by the learning block based on one or more measured characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.

    DRIVE CIRCUIT FOR AN OSCILLATOR
    8.
    发明申请

    公开(公告)号:US20170104454A1

    公开(公告)日:2017-04-13

    申请号:US15270652

    申请日:2016-09-20

    IPC分类号: H03B5/32

    摘要: The present invention concerns a drive circuit for driving an oscillator. The drive circuit comprises a first inductor comprising a first terminal and a second terminal; an electrical energy source connected to the first terminal; and a switching circuit connected to the second terminal and to the oscillator. The switching circuit is configured to operate at least in an off state, where it is configured not to feed electrical energy to the oscillator, and in an on state, where it is configured to feed electrical energy to the oscillator. The first inductor is arranged to store energy in its magnetic field when the switching circuit is in the off state, and, when the switching circuit is in the on state, the switching circuit is arranged to use at least some of the energy stored in the magnetic field to deliver a surge of current from the electrical energy source to the oscillator.

    Frequency synthesizers with adjustable delays
    9.
    发明授权
    Frequency synthesizers with adjustable delays 有权
    具有可调延迟的频率合成器

    公开(公告)号:US09590646B1

    公开(公告)日:2017-03-07

    申请号:US14836797

    申请日:2015-08-26

    申请人: NXP B.V.

    摘要: A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.

    摘要翻译: 射频(RF)信号可以产生具有响应于频率参考(FREF)时钟的RF频率。 电感电容(LC)振荡电路可以产生RF信号。 对于FREF时钟的第一边缘,数字到时间转换器(DTC)电路可以在具有第一延迟的基线模式中以及在FREF时钟的后续边沿处以引入第二延迟的延迟模式 值到FREF时钟。 控制器电路可以响应于FREF时钟的第一边缘而使LC-槽振荡器电路能够设置或增加作为RF信号的频率的函数的延迟模式的第二延迟值。 相位检测器电路可以检测FREF时钟的后续边沿FREF时钟和RF信号之间的相位差。

    VOLTAGE CONTROLLED OSCILLATOR RUNAWAY PREVENTION
    10.
    发明申请
    VOLTAGE CONTROLLED OSCILLATOR RUNAWAY PREVENTION 有权
    电压控制振荡器RUNAWAY预防

    公开(公告)号:US20160285466A1

    公开(公告)日:2016-09-29

    申请号:US14671259

    申请日:2015-03-27

    IPC分类号: H03L7/085

    摘要: A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

    摘要翻译: 用于防止锁相环(PLL)电路中的压控振荡器(VCO)失控的反馈模块可以包括第一,第二和第三输入端,以从PLL电路接收第一输出信号,参考信号和 第一控制信号。 反馈模块还可以包括用于产生第二控制信号的反馈电路,第二控制信号耦合到PLL电路的输入端,其中反馈电路通过比较第一输出信号的周期数来产生第二控制信号 到第一阈值,以及参考信号的周期数到第二阈值。